Identifying Platform Clocks - 2024.2 English - UG1700

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID
UG1700
Release Date
2025-01-15
Version
2024.2 English

Scalable Clocks (AMD Alveo™ Platforms only)

Note: See Embedded Design Development Using Vitis (UG1701) for Platform Clocks information.

An AMD Alveo platform provides a frequency scalable kernel clock with ID (or Index) 0 that drives all XRT managed kernels. XRT can set the clock frequency of this clock according to the metadata contained in the xclbin file, when loading the file. An Alveo platform also provides a second scalable clock with ID 1 that is also controllable based on xclbin metadata. You do not need to provide an option to connect to scalable clocks, but you can specify the clock frequency during v++ linking using the --freqhz option or --kernel_frequency, as described in v++ General Options in the Vitis Reference Guide (UG1702). The v++ linker automatically connects PL kernel clocks ap_clk to clock ID 0, and ap_clk2 to clock ID 1.

Tip: In practice, ap_clk2 is primarily found on RTL kernels, because the HLS compiler does not generate kernels with multiple clocks.

You can determine the clocks available in the target platform by using the platforminfo command.

=================
Clock Information
=================
  Default Clock Index: 2
  Default Clock Frequency: 312.499712
  Default Clock Pretty Name: PL 2
  Clock Index:         0
    Frequency:         156.249856
    Status:            fixed
    Name:              clk_wizard_0_clk_out2
    Pretty Name:       PL 0
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            6.400006
    Normalized Period: .006400
  Clock Index:         1
    Frequency:         104.166570
    Status:            fixed
    Name:              clk_wizard_0_clk_out1
    Pretty Name:       PL 1
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            9.600009
    Normalized Period: .009600
  Clock Index:         2
    Frequency:         312.499712
    Status:            fixed
    Name:              clk_wizard_0_clk_out3
    Pretty Name:       PL 2
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            3.200003
    Normalized Period: .003200
  Clock Index:         3
    Frequency:         78.124928
    Status:            fixed
    Name:              clk_wizard_0_clk_out4
    Pretty Name:       PL 3
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            12.800012
    Normalized Period: .012800
  Clock Index:         4
    Frequency:         208.333141
    Status:            fixed
    Name:              clk_wizard_0_clk_out5
    Pretty Name:       PL 4
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            4.800004
    Normalized Period: .004800
  Clock Index:         5
    Frequency:         416.666283
    Status:            fixed
    Name:              clk_wizard_0_clk_out6
    Pretty Name:       PL 5
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            2.400002
    Normalized Period: .002400
  Clock Index:         6
    Frequency:         624.999425
    Status:            fixed
    Name:              clk_wizard_0_clk_out7
    Pretty Name:       PL 6
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            1.600001
    Normalized Period: .001600