Hardware emulation runs an RTL simulation of the programmable logic design, where the PL kernels are integrated with a cycle-approximate model of the hardware platform.
Hardware emulation is especially useful for the following tasks:
- Checking the functional correctness of the RTL code synthesized from the C, C++ kernel code
- Testing the interactions between different kernels or multiple CUs
- Using hardware waveforms to gain detailed visibility into internal activity of the kernels
- Getting initial performance estimates for the application
- C/++ or Python traffic generators can be used to inject traffic in the simulation
Each kernel is compiled to a hardware model (RTL). During hardware emulation, kernels are run in the logic simulator, with a waveform viewer to examine the kernel design. Some third-party simulators are also supported as described in Simulator Support in Hardware Emulation. In addition, hardware emulation provides performance and resource estimates for the hardware implementation.
Hardware emulation provides a detailed, cycle-accurate, view of kernel activity. AMD recommends using small data sets for validation during hardware emulation to keep runtimes manageable.
As discussed in
v++
Command in the Vitis
Reference Guide (UG1702), the
hardware emulation target is specified in the v++ command with
the -t option:
v++ -t hw_emu ...