HW Interfaces - 2024.2 English - UG1700

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID
UG1700
Release Date
2025-01-15
Version
2024.2 English

The kernel interfaces are used to exchange data with the host application, other kernels, or device I/Os. Both user-managed and XRT-managed have exactly the same interface requirements as listed here:

Programmable interface
AXI4-Lite slave interface. Kernels can only have a single AXI4-Lite interface.
Data interfaces
Any number and combination of AXI4 memory mapped and AXI4-Stream interfaces.
Clock and resets
As described in Clock and Reset Requirements.
Tip: XRT-managed kernels have specific requirements for control registers in the AXI4-Lite interface (including start and stop bits) as described in Control Requirements for XRT-Managed Kernels. User-managed kernels can implement whatever control scheme the user specifies.

The following table elaborates the type of interface required based on the characteristics of the data movement in your application.

Table 1. Kernel Interface Types
Register (AXI4-Lite) Memory Mapped (M_AXI) Streaming (AXI4-Stream)
  • Register interfaces must be implemented using a single AXI4-Lite interface.
  • Designed for transferring scalars between the host application and the kernel.
  • Register reads and writes are initiated by the host application.
  • The kernel acts as a slave.
  • Memory mapped interfaces must be implemented using one or more AXI4 Masters interfaces.
  • Designed for bi-directional data transfers with global memory (DDR, PLRAM, HBM).
  • Introduces additional latency for memory transfers.
  • The kernel acts as a master accessing data stored into global memory.
  • The host application allocates the buffer for the size of the dataset.
  • The base address of the buffer is provided by the host application to the kernel via the AXI4-Lite interface.
  • Streaming interfaces must be implemented using one or more AXI4-Stream interfaces.
  • Designed for uni-directional data transfers between kernels.
  • The access pattern is sequential.
  • Does not use global memory.
  • Data set is unbounded.
  • A sideband signal can be used to indicate the last value in the stream.