In the Vitis core development
kit, Alveo Data Center acceleration cards
provide a foundation for designs. These devices contain a programmable logic (PL)
region that loads and executes a device binary (.xclbin) file that contains and connects PL kernels as compiled object
(.xo) files.
Extensible Alveo acceleration card
contain one or more interfaces to global memory (DDR or HBM), and optional streaming interfaces connected to other resources
such as external I/O. PL kernels can access data through global memory interfaces
(m_axi) or streaming interfaces (axis). The memory interfaces of PL kernels must be
connected to memory interfaces of the extensible platform. The streaming interfaces
of PL kernels can be connected to any streaming interfaces of the platform, of other
PL kernels. Both memory-based and streaming connections are defined through Vitis linking options, as described in Linking the System.
Multiple kernels (.xo) can be implemented in the PL region of the AMD device binary (.xclbin), allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances, or compute units of a kernel is programmable up to 31, and determined by linking options specified when building the device binary.