Clock and Reset Requirements - 2025.1 English

Clock and Reset Requirements - 2025.1 English - UG1700

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID

UG1700

Release Date

2025-05-29

Version

2025.1 English

These clock and reset requirements apply to both software controllable and non-software controllable kernels.

Table 1. Requirements
C/C++/OpenCL C Kernel	RTL Kernel
C kernel does not require any input from user on clock ports and reset ports. The HLS tool always generates RTL with clock port `ap_clk` and reset port `ap_rst_n`. HLS kernels can only have one clock/reset.	RTL kernels require at least one clock port, but a kernel can have multiple clocks. The number of clocks that an RTL can have is primarily determined by the number of clocks that the platform supports. Most data center platforms only support two clocks. An active-Low reset port can optionally be associated with a clock through the ASSOCIATED_RESET parameter on the clock.