Assigning AXI Interfaces to PLRAM - 2024.2 English - UG1700

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID
UG1700
Release Date
2025-01-15
Version
2024.2 English

For platforms that support PLRAM use the --connectivity.sp option as previously described in Mapping Kernel Ports to Memory, but use the name PLRAM[id] to specify the bank. Valid PLRAM banks supported by a platform can be found in the Memory Information section reported by the platforminfo command.

For example, in the Alveo U250 platform the following PLRAM information is reported:

  Bus SP Tag: PLRAM
    Segment Index: 0
      Consumption: explicit
      SLR:         SLR0
      Max Masters: 60
    Segment Index: 1
      Consumption: explicit
      SLR:         SLR1
      Max Masters: 60
    Segment Index: 2
      Consumption: explicit
      SLR:         SLR2
      Max Masters: 60
    Segment Index: 3
      Consumption: explicit
      SLR:         SLR3
      Max Masters: 60

To access the PLRAM you would use the following command for example:

--connectivity.sp cnn_1.weights:PLRAM3
Tip: To reduce latency and improve performance, the kernel accessing this PLRAM should be placed into SLR3 in addition to assigning compute units to SLRs. For more information, see Assigning Compute Units to SLRs on Alveo Accelerator Cards in the Data Center Acceleration using Vitis (UG1700).