This section describes the P4 actions in the Hello World Reference Pipeline using an example NACL table and rules set in it. Each row in the table represents a packet flow and each packet flow is described using a packet flow diagram.
Index | DMAC | SIP | DIP | SPORT | DPORT | Action |
---|---|---|---|---|---|---|
0 | 00:00:00:00:10:02 | 1.2.3.4 | 2.3.4.5 | 345 | 456 | Redirect |
1 | 00:00:00:00:10:04 | 5.5.5.5 | 1.2.1.2 | 486 | 524 | Permit |
2 | 00:50:00:00:10:23 | 3.5.6.2 | 4.2.0.8 | 989 | 835 | Drop |
* | * | * | * | * | * | Drop 1 |
|
The Pipeline highlights some of the basic capabilities of P4 and implements the following actions when a packet matches all the attributes:
- Redirect – Rule Match
- Packet is sent to
Arm®
Data Path
Application (DPA) Software for further processing.Note: This reference pipeline does not have accompanying DPA code and so packets sent to the Arm CPU complex for processing using the pipeline Redirect action are dropped.
- Packet is sent to
Arm®
Data Path
Application (DPA) Software for further processing.
- Permit – Rule Match
- If a packet is received on the DPU port Eth 1/1, it is sent out on port Eth 1/2.
- If a packet is received on the DPU port Eth 1/2, it is sent out on port Eth 1/1.
- Drop – Rule Match
- Packet is dropped.
- Drop - No Rule Match
- Packet is dropped
The packet header and payload is not sent through the stages; instead, the parser (a fully P4 programmable parser) creates a Packet Header Vector (PHV) from the packet header. The PHV is also stored in the Packet Buffer (PB). Only the reference to the PHV is used for processing by Ingress/Egress stages. This is done prior to stage 0 in Ingress. The payload stays in PB but is accessible from all stages. Only when a payload needs to be processed by an Arm CPU it is copied from/to PB to/from the Arm memory by a separate DMA engine. This transfer is initiated by a stage in the P4 RxDMA, or P4 TxDMA.