System Device Tree Output Directory - 2024.1 English

Porting Guide for embeddedsw Components System Device Tree Based Build Flow (UG1647)

Document ID
UG1647
Release Date
2024-06-21
Version
2024.1 English

The generated dts directory can contain following files:

  • soc.dtsi, which is a static SoC-specific file:
    • versal.dtsi for AMD Versal™ adaptive SoCs
    • zynqmp.dtsi for AMD Zynq™ UltraScale+™ MPSoCs
    • zynq-7000.dtsi for AMD Zynq™ 7000 devices
    Note: An SoC-specific dtsi file is not available for MicroBlaze processors.
  • pl.dtsi which contains information about soft IPs.
  • board.dtsi, which is board specific. This is required only when the -board_dts option is set. For example: versal-vck190-rev1.1.dtsi for the Versal VCK190 board, zcu102-rev1.0.dtsi for the Zynq UltraScale+ MPSoC ZCU102 board, zc702.dtsi for the Zynq 7000 ZCU102 board, and kc705-lite.dtsi for MicroBlaze processors.
  • clk.dtsi, which contains clocking information. For example, versal-clk.dtsi for Versal devices, zynqmp-clk-ccf.dtsi for Zynq UltraScale+ MPSoC devices. There are no clock framework files for Zynq 7000 devices and MicroBlaze processors.
  • system-top.dts, which is a top level system information which contains memory, clusters, and aliases.
  • pcw.dtsi, which contains peripheral configuration wizard information for the peripherals.
  • psu_init* files for Zynq 7000 and Zynq UltraScale+ MPSoCs, and pdi files for Versal devices.
  • For Versal designs, a folder with design name that contains the pdi_files contents.
Note: For more information on system device tree generation, see System Device Tree Generator (SDTGen / DTG++).