The procedure for resetting and reloading the AI Engine array facilitates the execution of applications on the
hardware platform multiple times without necessitating a full board and Linux operating
system reboot. This operation allows for the resetting and reloading of the AI Engine array, along with all programmable
logic (PL) components within the dynamic region block design. The reset and reload
sequence is conducted under the control of the RST_PL RESET0
register,
as detailed in the
Versal Adaptive SoC Register Reference (AM012). The key steps of the reset
and reload procedure encompass the following:
- Resetting the AI Engine array, which has been pre-configured with a specific AI Engine graph application, including kernels designated for specific tiles, DMA controllers, and the intercommunication between tiles and memory.
- Resetting the AI Engine array in cases where it operates on a non-DFx platform.
- Resetting the AI Engine array without necessitating a complete board reboot.
- Reloading the AI Engine array with either the same AI Engine graph or an alternative graph, all achieved without the need for a full board reboot.
In the course of consecutive resets and reloads of an application, it is imperative to maintain consistency in the AI Engine-PL interfaces. You have the flexibility to reload the AI Engine array with the same graphs used in the initial configuration or choose different graphs as required.
For more details on rest and reload for AI Engine, see the AI Engine Tools and Flows User Guide (UG1076).