Linux FPGA Manager - 2024.1 English

AI Engine System Software Driver Reference Manual (UG1642)

Document ID
UG1642
Release Date
2024-05-30
Version
2024.1 English

The FPGA manager exports a set of functions for programming an FPGA with an image at runtime. You can use the FPGA manager to reprogram an FPGA region with different images at runtime. The FPGA manager supports device tree overlay, which allows you to load different PL IPs with a different FPGA configuration for an FPGA region at runtime. The FPGA manager loads PDI by sending the Versal platform loader and manager (PLM) load requests with the PDI memory location to PLM. As the AI Engine configuration sequence is generated into CDO, which is packed into the PDI by AMD Vitis™ , use the FPGA manager to load AI Engine configuration or the AI Engine configuration plus PL configuration PDI at runtime. The FPGA manager framework disables the FPGA bridge so the traffic stops between the two sides of the bridge before programing a region connected to the bridge. Each AI Engine partition has AI Engine interface tiles row which can be used as FPGA bridge to connect AI Engine partition and the FPGA region. When the AI Engine FPGA region or the connected PL FPGA region needs reprogramming, the AI Engine FPGA bridge is disabled first.

Figure 1. AI Engine Partition and FPGA Manager

The PL FPGA region and AI Engine bridges connection are described in a device tree. The AI Engine device tree example is as follows:

ai_engine@20000000000 {
                        #address-cells = <0x02>;
                        #size-cells = <0x02>;
                        clock-names = "aclk0";
                        clocks = <0x15>;
                        compatible =