There exist four NPI interrupts designated as NPI interrupt for the AI Engine: 4, 5, 6, and 7. NPI interrupt 4 is directed towards the PMC EAM non-correctable line. NPI interrupt 5 is directed towards the PMC EAM correctable line, the PPU1, APU, and RPU. NPI interrupt 6 is directed towards PPU1, APU, RPU, and debug STM. Lastly, NPI interrupt 7 is routed to PPU1, APU, and RPU. The sole interrupts channeled to the PMC encompass PLL lock loss and scan clear. Any interrupts stemming from AI Engine error events are consistently captured and managed by the AI Engine driver and its corresponding application. In contrast, the programmable logic manager (PLM) does not capture these errors, and hence, does not need to monitor these interrupts.
NPI interrupts 5, 6, and 7 serve as channels for the APU and RPUs to monitor events originating from the AI Engine. Each processor makes use of one of these interrupts. Consequently, all events generated within the AI Engine partitions are directed to the processor associated with the same NPI interrupt. Notably, there is no sharing of interrupts among the control processors of the AI Engine. In cases where the PL is in charge of AI Engine control instead of the processing system (PS), events can be directly routed to the PL controller. Given the potentially extensive number of tiles to inspect when an interrupt occurs, particularly in a multi-threaded system like Linux, it is essential to ensure that event tracking takes place outside of the interrupt context.