AIE-ML Boot Sequence - 2024.1 English

AI Engine System Software Driver Reference Manual (UG1642)

Document ID
UG1642
Release Date
2024-05-30
Version
2024.1 English

This section outlines the procedural steps entailed in initiating the boot process for the AIE-ML array:

  1. Initially, the column clock enable value remains in a disabled state by default.
  2. A hardware logic component responsible for memory zeroization is introduced. It operates on both tile data memory and memory tile data memory within each tile program memory. For each of these memories, there exists a 1-bit memory-mapped AXI4 register, which is set to 1 when the zeroization process commences. Once this process is complete, the internal hardware resets this bit to 0.
  3. The power-on phase, accompanied by the deassertion of power-on-reset (POR): Power is activated for all modules connected to the AIE-ML array, including the PLL. After the power-on event, the PLL runs at a predefined default speed. Prior to initiating the AIE-ML boot sequence, it is imperative that both the platform management controller (PMC) and network-on-chip (NoC) components are operational. Once the array is powered up, the PMC can proceed to deassert the POR signal within the AIE-ML array.
  4. Configuration of the AIE-ML array using network programming interface (NPI): Subsequent to the power-on phase, the PMC uses the NPI interface to configure various global registers within the AIE-ML array, such as the PLL configuration registers. The necessary AIE-ML configuration image for the initialization of the array is sourced from a flash device.
  5. Enabling the PLL: Following the configuration of PLL registers (post-POR), the PLL-enable bit can be activated to initiate the PLL. The PLL subsequently stabilizes at the programmed frequency and asserts the LOCK signal. The source of the PLL input (ref_clk) is derived from hsm_ref_clk and is generated within the control interfaces and processing system (CIPS). For comprehensive details on clock generation and distribution, see the PMC and PS Clocks chapter within the Versal Adaptive SoC Technical Reference Manual (AM011).
  6. Assertion and de-assertion of column clock and column reset signals: Once the PLL achieves lock, all column clocks are activated by setting a specific bit in a memory-mapped AXI4 register to 1. Subsequently, all column resets are initiated by writing a 1 to another memory-mapped AXI4 register bit. After a designated number of cycles, all column resets are deactivated by setting the same register bit to 0.
  7. The array is divided into one or more independent partitions, each consisting of an integer number of AI Engine columns. Isolation is automatically enabled in all tiles by default, so it must be disabled at the internal edges of each partition.
  8. Programming of the AIE-ML array: The AIE-ML array interface configuration is accomplished via the memory-mapped AXI4 interface from the NoC interface. This encompasses the configuration of all program memories, AXI4-Stream switches, DMAs, event settings, and trace configuration registers.

The AI Engine array is hardcoded to be non-secure in the CDO and needs to be set based on the AMD Vivado™ configuration. The AI Engine data memory zeroization is an AI Engine ELF embedded in the PLM code, the CDO request for AI Engine memory initialization function. The PLM calls the AI Engine domain memory initialization function to do the following:

  • Enable ECC scrubbing and reset the AI Engine array.
  • Load the zeroization code to each tile and run it to clear the memory.
  • Reset the AI Engine array.