AI Engine Boot Sequence - 2024.1 English

AI Engine System Software Driver Reference Manual (UG1642)

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2024.1 English

The power on reset boot sequence is defined in aie_engin_data.cdo. This CDO is generated by AMD Vivado™ if there is an AI Engine device connected in the system and is part of boot PDI. This section describes the steps involved in the boot process for the AI Engine array.

  1. Power-on and power-on-reset (POR) deassertion: Power is turned on for all modules related to the AI Engine array, including the PLL. After power-on, the PLL runs at a default speed. The platform management controller (PMC) and NoC need to be up and running before the AI Engine boot sequence is initiated. After the array power is turned on, the PMC can deassert a POR signal in the AI Engine array.
  2. AI Engine array configuration using NPI: After power-on, the PMC uses the NPI interface to program the different global registers in the AI Engine array (for example, the PLL configuration registers). The AI Engine configuration image that is required over the NPI for AI Engine array initialization comes from a flash device.
  3. Enable PLL: Once the PLL registers are configured (after POR), the PLL-enable bit can be enabled to turn on the PLL. The PLL then settles on the programmed frequency and asserts the LOCK signal. The source of the PLL input (ref_clk) is from hsm_ref_clk and is generated in the control interfaces and processing system (CIPS). The generation and distribution of the clock is described in the PMC and PS Clocks chapter of the Versal Adaptive SoC Technical Reference Manual (AM011).
  4. Release reset: Once the PLL is locked, software can program a register to deassert the global reset signal for the AI Engine array.
  5. AI Engine array programming: The AI Engine array interface needs to be configured over the memory-mapped AXI4 from the NoC interface. This includes all AXI4-Stream switches, memory-mapped AXI4 switches, array interface DMAs, event, and trace configuration registers.