UltraScale+ Device Configuration

Alveo U45N Data Center Accelerator Card User Guide (UG1636)

Document ID
Release Date
1.0 English

The AlveoU45N accelerator card supports two UltraScale+™™ FPGA configuration modes:

  • Quad SPI flash memory
  • JTAG using ADK2 configuration port

The FPGA bank 0 mode pins are hardwired to master SPI mode M[2:0] = 001 with pull-up/down resistors.

At power up, the FPGA is configured by the Quad SPI NOR flash device using the primary serial configuration mode. Refer to the XDC for recommended configuration parameters specified via the various BITSTREAM.CONFIG constraints.

If the JTAG cable is plugged in, QSPI configuration might not occur. JTAG mode is always available independent of the mode pin settings.

For complete details on configuring the FPGA, see the UltraScale Architecture Configuration User Guide (UG570).

Table 1. Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 FPGA output
JTAG Not applicable – JTAG overrides x1 Not applicable