This system represents a typical use case in which the system is required to monitor error frequency, and to generate an interrupt to immediately correct a single bit error through software. It does not provide support for testing of the ECC function.
It is a small system with Correctable Error First Failing registers and a Status register added. A single bit error latches the address for access into the Correctable Error First Failing Address register, and sets the CE_STATUS bit in the ECC Status register. An interrupt is generated, triggering MicroBlaze to read the failing address and then perform a read followed by a write on the failing address. This removes the single bit error from the block RAM, thus reducing the risk of the single bit error becoming a uncorrectable double bit error. The parameters set are as follows:
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C_ECC= 1 -
C_CE_COUNTER_WIDTH= 10 -
C_ECC_STATUS_REGISTER= 1 -
C_CE_FAILING_REGISTERS= 1