The translation look-aside buffer (TLB) is used by the MicroBlaze V MMU for address translation when the processor is running in virtual mode, memory protection, and storage control. Each entry within the TLB contains the information necessary to identify a virtual page (ASID and virtual page number), specify its translation into a physical page, determine the protection characteristics of the page, and specify the storage attributes associated with the page.
The MicroBlaze V TLB is physically implemented as three separate TLBs:
- Unified TLB
- The UTLB contains 64 entries and is pseudo-associative. Instruction-page and data-page translation can be stored in any UTLB entry. The initialization and management of the UTLB is controlled by hardware, which reads information from the page tables stored in memory.
- Instruction Shadow TLB
- The ITLB contains instruction page-translation entries and is fully associative. The page-translation entries stored in the ITLB represent the most recently accessed instruction-page translations from the UTLB. The ITLB is used to minimize contention between instruction translation and UTLB-update operations. The initialization and management of the ITLB are controlled completely by hardware and are transparent to software.
- Data Shadow TLB
- The DTLB contains data page-translation entries and is fully associative. The page-translation entries stored in the DTLB represent the most-recently accessed data-page translations from the UTLB. The DTLB is used to minimize contention between data translation and UTLB-update operations. The initialization and management of the DTLB is controlled completely by hardware and is transparent to software.
The following figure provides the translation flow for TLB.
Two schemes to manage accessed (A) and dirty (D) bits are permitted by the virtual memory system. MicroBlaze V implements the first scheme, raising a page-fault exception when a virtual page is accessed and the A bit is clear, or is written and the D bit is clear.
MicroBlaze V implements the Supervisor Memory-Management Fence Instruction (SFENCE.VMA) to ensure ordering and invalidate entries in the TLB.