The following table lists the Trace Encoder Control Register implemented fields. The optional fields trTeInstTrigEnable and TrTeInstStallEna are not implemented.
Figure 1. Trace Encoder Control Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 26:24 | trTeFormat | 1: Format defined by RISC-V N-Trace (Nexus-based Trace) Specification. Read only. | 001 |
| 23:20 | trTeInstSyncMax | The maximum interval between instruction trace synchronization messages, with unit trace messages. | 0000 |
| 17:16 | trTeInstSyncMode | Select the periodic instruction trace
synchronization message generation mechanism. 0: Off 1: Count trace messages. Other generation mechanisms are not supported. |
00 |
| 15 | trTeInhibitSrc | 1: Disable inclusion of source field in trace messages. | 0 |
| 12 | trTeInstStallOrOverflow | Set to 1 by hardware when trace buffer overflow occurs. Clears to 0 at reset or when the trace is enabled. Write 1 to clear. | 0 |
| 9 | trTeContext | Enable sending trace messages/fields with privilege levels | 0 |
| 6:4 | trTeInstMode |
Instruction trace generation mode 0: Full Instruction trace is disabled. 3: Baseline instruction trace (Branch Trace Messaging). 6: Optimized instruction trace (History Trace Messaging). Other generation modes are not supported. |
000 |
| 3 | trTeEmpty | Reads as 1 when all generated trace are emitted. Read only. | 0 |
| 2 | trTeInstTracing | 1: Instruction trace is being generated. | 0 |
| 1 | trTeEnable | 1: Trace Encoder is enabled. | 0 |
| 0 | trTeActive | Primary activate/reset bit for the TE. | 0 |