The Timestamp Control Register implemented fields are listed below. Only the Internal Core mode is implemented.
Figure 1. Timestamp Control Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 29:24 | trTsWidth | Width of timestamp in bits (0..63). | 000000 |
| 15 | trTsEnable | Enable for timestamp field in trace messages. | 0 |
| 9:8 | trTsPrescale |
Prescale timestamp input clock by dividing by 1, 4, 16, or 64. |
00 |
| 6:4 | trTsMode | Mode used by Timestamp unit: Read only. 3: Internal Core |
011 |
| 3 | trTeRunInDebug |
1: counter runs when hart is halted (in debug mode), 0: stopped |
0 |
| 2 | trTsReset | Write 1 to reset the timestamp counter. Write only. | 0 |
| 1 | trTsCount |
1: counter runs, 0: counter stopped. |
0 |
| 0 | trTsActive | Primary activate/reset bit for timestamp unit. | 0 |