RISC-V terminology used in this guide is briefly explained in the following list, as it pertains to the MicroBlaze V processor. Refer to the RISC-V Instruction Set Manual for a complete and comprehensive explanations of the terms.
- Custom Instruction
- An instruction set category available for vendor-specific non-standard extensions. MicroBlaze V defines GET and PUT custom instructions to support AXI4-Stream interfaces and extended address load/store instructions, providing compatibility with classic MicroBlaze.
- Exception
- An unusual condition occurring at runtime associated with an instruction in the current RISC-V hart.
- Hart
- Hardware thread. Each MicroBlaze V core only supports one hart.
- Interrupt
- An external asynchronous event that can cause a RISC-V hart to experience an unexpected transfer of control. MicroBlaze V supports machine external interrupt, non-maskable interrupt, and custom platform interrupt.
- Retire
- An instruction is said to retire when its execution completes. In MicroBlaze V, instructions are retired when they leave the execute (EX) pipeline stage for the 3-stage pipeline, or the writeback (WB) pipeline stage for all other pipelines.
- Trap
- The transfer of control to a trap handler caused by either an exception or an interrupt.