The parameter C_LOCKSTEP_SLAVE is set to 1 on
all slave MicroBlaze V cores in the system, except the
master (or primary) core. The master core drives all the output signals, and handles the
debug functionality. The port Lockstep_Master_Out on
the master is connected to the port Lockstep_Slave_In
on the slaves to handle debugging.
The slave cores should not drive any output signals, and should only receive input signals. This constraint must be ensured by only connecting signals to the input ports of the slaves. For buses, this means that each individual input port must be explicitly connected.
The port Lockstep_Out on the master and slave cores provide all
output signals for comparison. Unless an error occurs, individual signals from each of
the cores are identical every clock cycle.
To ensure that lockstep operation works properly, all input signals to the cores
must be synchronous. Input signals that could require external synchronization are
Interrupt, Ext_Brk,
Ext_NM_Brk, and Reset.