Scrubbing is performed using specific methods for the different block RAMs:
- Branch target cache
- The entire BTC is invalidated by doing a
fence.iinstruction. - LMB block RAM
- All addresses in the memory are cyclically read and written, thus correcting any single bit errors on each address.
It is also possible to add interrupts for correctable errors from the LMB BRAM Interface Controllers, and immediately scrub this address in the interrupt handler, although in most cases it only improves reliability slightly.
The failing address can be determined by reading the Correctable Error First Failing Address register in each of the LMB BRAM Interface Controllers.
To generate an interrupt, C_ECC_STATUS_REGISTERS must be set to 1 in the connected LMB BRAM
Interface Controllers. To read the failing address, C_CE_FAILING_REGISTERS must be set to 1.