Figure 1. Store Byte Extended Address
Description
Stores the least significant byte of register rs2, into the byte memory location accessed by the effective address formed by concatenating the contents of registers rs1 and rs1+1. The rs1 register number must be even. Use of a misaligned (odd-numbered) register is reserved.
A store/AMO access fault exception occurs in the case of an unsuccessful Physical Memory Access (PMA) check, or in the case of errors when writing data to memory.
A store/AMO page fault exception is caused by an unsuccessful virtual memory effective address translation.
Pseudocode
Addr ← (rs1 + 1) (rs1)
Mem(Addr) ← (rs2)[24:31]Registers Altered
None
Latency
- One cycle with
C_OPTIMIZATION= 0, 2, 3 - Two cycles with
C_OPTIMIZATION= 1
Notes
- The instruction is only valid if MicroBlaze V is configured to use extended address with PMP disabled (C_ADDR_SIZE > 32, C_PMP_ENTRIES = 0) and with RV32I Base Integer Instruction Set (C_DATA_SIZE = 32).
- Instruction bits 7-11, 26-28 and 31 are ignored when decoding the instruction.