When a Reset or Debug_Rst occurs, MicroBlaze V flushes the
pipeline and immediately starts fetching instructions from the reset vector (address
C_BASE_VECTORS). Both external reset signals are
active-High, and it is recommended to assert the signals for at least 16 cycles.
Reset does not clear the general purpose registers (x1 – x31), the floating-point registers (f0 – f31), or the PMP address registers (pmpaddr0 – pmpaddr63) . To ensure that stale data is not used, software should not assume that the general purpose registers or floating-point registers are zero.
MicroBlaze V does not wait for outstanding
AXI or LMB transactions to complete before it begins fetching instructions from the
reset vector. When only resetting the processor, all external accesses must be completed
before asserting Reset. This can be achieved with a
wfi instruction to enter sleep mode or the Pause signal. See Sleep and Pause Functionality for details.
Equivalent Pseudocode
pc ← C_BASE_VECTORS
fcsr ← 0
mstatus ← 0, 00020000, 00018000, 00038000
mie ← 0; mtvec[31:2] ← (C_BASE_VECTORS + 4) / 4; mtvec[1:0] ← 00
mcounteren ← 0; mscratch ← 0; mepc ← 0; mcause ← 0; mtval ← 0
mstream ← 0; mwfi ← 0
mcycle ← 0; minstret ← 0;
mcycleh ← 0; minstreth ← 0; mhpmcounterh3 - mhpmcounterh31 ← 0
mcountinhibit ← 0;
cycle ← 0; instret ← 0;
cycleh ← 0; instreth ← 0; hpmcounterh3 - hpmcounterh31 ← 0
Reservation ← 0The actual mstatus reset value depends on parameters. See the Machine Status Register (mstatus) description for details.
The actual mhpmevent, mhpmcounter, and hpmcounter reset values depend on the configured debug event counters and debug latency counters. For details, see the description in Table 1.