Reset, Interrupts, and Exceptions - 2025.2 English - UG1629

MicroBlaze V supports reset, interrupt, and hardware exceptions according to the RISC-V Instruction Set Manual. The non-maskable interrupt is supported using the external input signal Ext_NM_BRK. A platform interrupt is defined using the external input signal Ext_BRK. The following section describes the execution flow associated with each of these events.

Normally, the reset vector is located at address 0, but the parameter C_BASE_VECTORS can be used to locate it anywhere in memory.

The memory address location of the trap vector is determined by the mtvec or stvec registers, which are initialized to C_BASE_VECTORS + 4 with the two least significant bits set to 00 but can be changed to any address by software.

The memory address location of the non-maskable interrupt vector is determined by the mnivec register available when C_TRAP_ENHANCEMENT > 1, which is initialized to C_BASE_VECTORS + 8 but can be changed to any address by the software.

The memory address location of the non-maskable exception vector is determined by the mnevec register available when C_TRAP_ENHANCEMENT > 1, which is initialized to C_BASE_VECTORS + 12 but can be changed to any address by the software.

The relative priority, starting with the highest, is:

1. Reset
2. Non-maskable interrupt
3. Platform interrupt
4. External interrupt
5. Breakpoint (instruction) exception
6. Instruction page fault exception
7. Instruction access fault exception
8. Illegal instruction, instruction address misaligned, environment call, breakpoint (data) exceptions
9. Load address misaligned, store/AMO address misaligned exceptions
10. Load page fault, store/AMO page fault exception
11. Load access fault, store/AMO access fault, AXI4-Stream exceptions

The priority between exceptions is compliant with the RISC-V Instruction Set Manual, Volume II.