Registers - 2025.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2025-07-09
Version
2025.1 English

MicroBlaze V implements registers according to the RISC-V Instruction Set Manual. All mandatory registers are implemented.

Implemented control and status registers (CSRs) are described here. For information on the general purpose registers and floating-point registers, see the RISC-V Instruction Set Manual.

Table 1. Control and Status Registers
Name Number Reset Value Access Remark
fflags 0x001 0x00000000 RW Exists if floating-point is enabled.
frm 0x002 0x00000000 RW Exists if floating-point is enabled.
fcsr 0x003 0x00000000 RW Exists if floating-point is enabled.
sstatus 0x100 - RW Exists if supervisor mode is enabled. Reset value depends on if floating-point is enabled. See Reset for details.
sie 0x104 0x00000000 RO Exists if supervisor mode is enabled.
stvec 0x105 C_BASE_VECTORS+4 RW Exists if supervisor mode is enabled.
scounteren 0x106 0x00000000 RW Exists if supervisor mode is enabled.
senvcfg 0x10a 0x00000000 RW Exists if supervisor mode is enabled.
sscratch 0x140 0x00000000 RW Exists if supervisor mode is enabled.
sepc 0x141 0x00000000 RW Exists if supervisor mode is enabled.
scause 0x142 0x00000000 RW Exists if supervisor mode is enabled.
stval 0x143 0x00000000 RW Exists if supervisor mode is enabled.
sip 0x144 0x00000000 RO Exists if supervisor mode is enabled.
satp 0x180 0x00000000 RW Exists if supervisor mode is enabled.
mstatus 0x300 - RW Reset value depends on if user mode, supervisor mode, and floating-point are enabled. See Reset for details.
misa 0x301 - RO Reset value depends on enabled extensions and modes. See Reset for details.
medeleg 0x302 0x00000000 RW Exists if supervisor mode is enabled.
mideleg 0x303 0x00000000 RO Exists if supervisor mode is enabled.
mie 0x304 0x00000000 RW  
mtvec 0x305 C_BASE_VECTORS+4 RW  
mcounteren 0x306 0x00000000 RW Exists if user mode is enabled.
menvcfg 0x30a 0x00000000 RW Exists if user mode is enabled.
mcountinhibit 0x320 0x00000000 RW  
mhpmevent 0x323 - 0x323+N 0x00000000 or 0x0000000A RW Read-only zero unless debug event or latency counters are enabled. Write is ignored when read-only.

Reset value is 0x0000000A for debug latency counters. N = 0 to 28.
mscratch 0x340 0x00000000 RW  
mepc 0x341 0x00000000 RW  
mcause 0x342 0x00000000 RW  
mtval 0x343 0x00000000 RW  
mip 0x344 - RO Reset value depends on inputs
pmpcfg 0x3a0 - 0x3a0+N 0x00000000 RW Exists if PMP entries > 0. N = 0 to 15 for RV32, and N = 0, 2, …, 14 for RV64.
pmpaddr 0x3b0 - 0x3b0+N 0x00000000 RW Exists if PMP entries > 0. N = 0 to 63.
mseccfg 0x747 0x00000000 RW Exists if PMP entries > 0 and PMP Enhancements are enabled.
tselect 0x7a0 0x00000000 RW Exists if debug is enabled.
tdata1 0x7a1 0x00000000 RW Exists if debug is enabled.
tdata2 0x7a2 0x00000000 RW Exists if debug is enabled.
tinfo 0x7a3 0x00000005 RO Exists if debug is enabled.
dcsr 0x7b0 0x40000603 RW Exists if debug is enabled, only accessible in debug mode
dpc 0x7b1 C_BASE_VECTORS RW Exists if debug is enabled, only accessible in debug mode
mstream 0x7c0 0x00000000 RW Custom CSR, exists if one or more AXI4-Streams are enabled
mwfi 0x7c4 0x00000000 RW Custom CSR, exists if more than one of sleep, hibernate, and suspend outputs are enabled
stream 0x8c0 0x00000000 RW Custom CSR, exists if one or more AXI4-Streams are enabled, user mode is enabled, and stream instructions are allowed
mcycle 0xb00 0x00000000 RW Read-only zero unless base counters and timers are enabled.
minstret 0xb02 0x00000000 RW Read-only zero unless base counters and timers are enabled.
mhpmcounter 0xb03 - 0xb03+N 0x00000000 or 0xFFFF0000 RW Read-only zero unless debug event or latency counters are enabled, and base counters and timers are enabled. Reset value is 0xFFFF0000 for debug latency counter min/max registers. N = 0 to 28.
mcycleh 0xb80 0x00000000 RW Read-only zero unless base counters and timers are enabled.
minstreth 0xb82 0x00000000 RW Read-only zero unless base counters and timers are enabled.
mhpmcounterh 0xb83 - 0xb83+N 0x00000000 RW Read-only zero unless debug event or latency counters are enabled, and base counters and timers are enabled. N = 0 to 28. Debug latency counter min/max registers are read-only zero.
cycle 0xc00 0x00000000 RO Read-only zero unless base counters and timers are enabled.
instret 0xc02 0x00000000 RO Read-only zero unless base counters and timers are enabled.
hpmcounter 0xc03 - 0xc03+N 0x00000000 or 0xFFFF0000 RO Zero unless debug event or latency counters are enabled, and base counters and timers are enabled. Reset value is 0xFFFF0000 for debug latency counter min/max registers. Write is ignored. N = 0 to 28.
cycleh 0xc80 0x00000000 RO Read-only zero unless base counters and timers are enabled.
instreth 0xc82 0x00000000 RO Read-only zero unless base counters and timers are enabled.
hpmcounterh 0xc83 - 0xc83+N 0x00000000 RO Zero unless debug event or latency counters are enabled, and base counters and timers are enabled. Write is ignored. N = 0 to 28. Debug latency counter min/max registers are read-only zero.
mvendorid 0xF11 0x00000049 RO  
marchid 0xF12 C_ARCHID RO  
mimpid 0xF13 C_IMPID RO  
mhartid 0xF14 C_HARTID RO  
mconfigptr 0xF15 0x00000000 RO Implemented, but zero

For CSRs with optional, implementation defined, features and for custom CSRs, descriptions are provided. For other registers, see the RISC-V Instruction Set Manual.