References - 2025.2 English - UG1629

These documents provide supplemental material useful with this guide:

1. The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA
2. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
3. RISC-V Debug Specification, Version 1.0
4. RISC-V N-Trace (Nexus-based Trace) Specification, Version 1.0
5. RISC-V Trace Control Interface Specification, Version 1.0
6. MicroBlaze V Processor Embedded Design User Guide (UG1711)
7. AMBA AXI and ACE Protocol Specification (Arm IHI 0022H)
8. MicroBlaze Debug Module (MDM) V LogiCORE IP Product Guide (PG428)
9. LMB BRAM Interface Controller LogiCORE IP Product Guide (PG112)
10. Soft Error Mitigation Controller LogiCORE IP Product Guide (PG036)
11. UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)
12. Triple Modular Redundancy (TMR) LogiCORE IP Product Guide (PG268)
13. Vitis Unified Software Platform Documentation Landing Page (UG1416)
14. Vivado Design Suite User Guide: Designing with IP (UG896)
15. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
16. Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
17. ELF: Tool Interface Standard (TIS) Executable and Linking Format (ELF) Specification
18. MicroBlaze Processor Reference Guide (UG984)
19. Device Reliability Report (UG116)