Read and Write Data Steering - 2025.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2025-07-09
Version
2025.1 English

The MicroBlaze V data-side bus interface performs the read steering and write steering required to support the following transfers:

  • Byte, half word, and word transfers to word devices
  • Byte and half word transfers to half word devices
  • Byte transfers to byte devices

MicroBlaze V does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the bus interface. Data steering for read and write cycles are shown in the following tables.

Table 1. Read Data Steering (Load to Register xD)
Address Byte Enable Transfer Size Register xD Data
xD[31:24] xD[23:16] xD[15:8] xD[7:0]
11 1000 byte       Byte0
10 0100 byte       Byte1
01 0010 byte       Byte2
00 0001 byte       Byte3
10 1100 halfword     Byte0 Byte1
00 0011 halfword     Byte2 Byte3
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 2. Write Data Steering (Store from Register xD)
Address Byte Enable Transfer Size Write Data Bus Bytes
Byte 3 Byte 2 Byte 1 Byte 0
11 1000 byte xD[7:0]      
10 0100 byte   xD[7:0]    
01 0010 byte     xD[7:0]  
00 0001 byte       xD[7:0]
10 1100 halfword xD[15:8] xD[7:0]    
00 0011 halfword     xD[15:8] xD[7:0]
00 1111 word xD[31:24] xD[23:16] xD[15:8] xD[7:0]
Note: Other masters could have more restrictive requirements for byte lane placement than those allowed by MicroBlaze V. Slave devices are typically attached “left-justified” with byte devices attached to the most significant byte lane, and half word devices attached to the most significant half word lane. The MicroBlaze V steering logic fully supports this attachment method.

When using 64-bit data on DLMB or M_AXI_DP with 64-bit MicroBlaze V, the following transfers are also supported:

  • byte, halfword, word, and long transfers to long devices

Data steering with 64-bit data for read cycles and 64-bit data steering for write cycles are shown in the following tables.

Table 3. Read Data Steering (Load to Register xD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Register xD Data
0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63
111 10000000 byte               Byte0
110 01000000 byte               Byte1
101 00100000 byte               Byte2
100 00010000 byte               Byte3
011 00001000 byte               Byte4
010 00000100 byte               Byte5
001 00000010 byte               Byte6
000 00000001 byte               Byte7
110 11000000 halfword             Byte0 Byte1
100 00110000 halfword             Byte2 Byte3
010 00001100 halfword             Byte4 Byte5
000 00000011 halfword             Byte6 Byte7
100 11110000 word         Byte0 Byte1 Byte2 Byte3
000 00001111 word         Byte4 Byte5 Byte6 Byte7
000 11111111 long Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7
Table 4. Write Data Steering (Store from Register xD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Write Data Bus Bytes from xD
Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
111 10000000 byte 56:63              
110 01000000 byte   56:63            
101 00100000 byte     56:63          
100 00010000 byte       56:63        
011 00001000 byte         56:63      
010 00000100 byte           56:63    
001 00000010 byte             56:63  
000 00000000 byte               56:63
110 11000000 halfword 48:55 56:63            
100 00110000 halfword     48:55 56:63        
010 00001100 halfword         48:55 56:63    
000 00000011 halfword             48:55 56:63
100 11110000 word 32:39 40:47 48:55 56:63        
000 00001111 word         32:39 40:47 48:55 56:63
000 11111111 long 0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63