The RAM Sink Control Register implemented fields are listed below. The optional field trRamAsyncFreq is not implemented.
Figure 1. RAM Sink Control Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 10:9 | trRamMemFormat | 00: Memory is formatted as plain bytes. Read only. | 00 |
| 8 | trRamStopOnWrap |
1: Disable storing trace when the circular buffer gets full. |
0 |
| 4 | trRamMode | 0: This RAM Sink operates in SRAM mode. Read only. SMEM mode is not supported. |
0 |
| 3 | trRamEmpty | Reads 1 when Trace RAM Sink internal buffers are empty. Read only. | 0 |
| 1 | trRamEnable | 1: Trace RAM Sink enabled. | 0 |
| 0 | trRamActive | Primary activate/reset bit for Trace RAM Sink. | 0 |