The effect of a data hazard is illustrated in the following table, using the 5-stage pipeline with the 32-bit implementation (RV32). The example shows a data hazard for a multiplication instruction, where the subsequent add instruction needs the result in register s0 to proceed. This means that the add instruction is stalled in OF during cycle 3 and 4 until the multiplication is complete.
| Cycle | IF | OF | EX | MEM | WB |
|---|---|---|---|---|---|
| 1 | Mul s0, s1, s2 | ||||
| 2 | Add s3, s0, s1 | Mul s0, s1, s2 | |||
| 3 | Add s3, s0, s1 | Mul s0, s1, s2 | |||
| 4 | Add s3, s0, s1 | Mul s0, s1, s2 | |||
| 5 | Add s3, s0, s1 | Mul s0, s1, s2 |