Peripheral Interfaces - 2025.1 English - UG1629

The MicroBlaze V AXI4 memory mapped peripheral interfaces are implemented as 32-bit masters. Each of these interfaces only have a single outstanding transaction at any time, and all transactions are completed in order.

• The instruction peripheral interface (M_AXI_IP) only performs single word read accesses, and is always set to use the AXI4-Lite subset.

• The data peripheral interface (M_AXI_DP) performs single word accesses, and is set to use the AXI4-Lite subset as default, but is set to use AXI4 when enabling exclusive access for lr and sc instructions. Halfword and byte writes are performed by setting the appropriate byte strobes. Each write transaction waits for M_AXI_DP_BVALID before the store instruction is completed.

The instruction peripheral interface (M_AXI_IP) address width is set according to the value of the parameter C_ADDR_SIZE.

The data peripheral interface (M_AXI_DP) address width is set according to the value of the parameter C_ADDR_SIZE.