PUTD - 2025.1 English - UG1629

Description

MicroBlaze V writes the value from register rs1 to the link interface defined by the four least significant bits of rs2.

The PUTD instruction has 16 variants.

The blocking versions (when n is 0) stall until there is space available in the interface. The non-blocking versions do not stall, and set the C bit in mstream to 0 if space is available, and to 1 if no space is available.

Except for the test versions, all data PUTD instructions (when c is 0) set the control bit to the interface to 0. All control PUTD instructions (when c is 1) set the control bit to 1.

The test versions (when the t bit is 1) are handled as normal, except that the data and control bit are not output and the write signal to the link is not asserted, and thus no source register is required, and link data is not assigned. The test version requires that rs1 is x0.

The atomic versions (when the a bit is 1) cannot be interrupted by a machine external interrupt or external break. Each atomic instruction prevents the subsequent instruction from being interrupted. This means that a sequence of atomic instructions can be grouped together without an interrupt breaking the program flow.

If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits of rs2, an illegal instruction exception occurs when C_ILL_INSTR_EXCEPTION = 2, otherwise the instruction behaves like a NOP.

Pseudocode

x ← rs2[3:0]
if x >= C_FSL_LINKS then
   if C_ILL_INSTR_EXCEPTION = 2 then 
      PC ← mtvec
      mcause ← 2
else
if t = 0 then
   Mx_AXIS_TDATA ← (rs1)
if n = 1 then
   mstream.C ← Mx_AXIS_TVALID ˄ Mx_AXIS_TREADY
if t = 0 then
   Mx_AXIS_TLAST ← c

Registers Altered

• mstream
• stream whenC_USE_MMU > 0
• PC and mcause, in case an illegal instruction exception is generated

Latency

• One cycle with C_OPTIMIZATION= 0, 2, 3
• Two cycles with C_OPTIMIZATION = 1

The blocking versions of this instruction stall the pipeline until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.

Notes

• These instructions are only available when the parameter C_FSL_LINKS is greater than 0.
• The extended instructions (test and atomic versions) are only available when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1.
• Instruction bits 7-11 and 25-27 are ignored when decoding the instruction.
• For the test version, rs1 is ignored when decoding the instruction.