The MicroBlaze V core is organized as a Harvard architecture with separate bus interface units for data and instruction accesses. The following three types of memory interfaces are supported: Local Memory Bus (LMB), and the AMBA® AXI4 interface (AXI4) and ACE interface (ACE).
The LMB provides single-cycle access to on-chip dual-port block RAM or UltraRAM. The AXI4 interfaces provide a connection to both on-chip and off-chip peripherals and memory. The ACE interfaces provide cache-coherent connections to memory.