A non-maskable interrupt is performed by asserting the external non-maskable
break signal (that is, the Ext_NM_BRK input port). On a
break, the instruction in the execution stage completes while the instruction in the
decode stage is replaced by a branch to the trap-vector base-address in mtvec.
The return address (the PC associated with the instruction in the decode stage at the time of the break) is automatically loaded into mepc. The mcause interrupt bit is set to 1 and the exception code is set to 0.
A non-maskable interrupt is always handled immediately.
The Ext_NM_BRK signal must only be asserted one clock cycle.
Equivalent Pseudocode
mepc ← PC
PC ← mtvec
mcause ← 0x80000000
mstatus.mpie ← mstatus.mie
mstatus.mie ← 0
if C_USE_MMU > 0
mstatus.mpp ← privilege mode
else
mstatus.mpp ← 11
mtval ← 0
Reservation ← 0