MicroBlaze V I/O Overview - 2025.2 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2025-11-20
Version
2025.2 English

The core interfaces shown in the following figure and table are defined as follows:

M_AXI_DP
Peripheral data interface, AXI4-Lite or AXI4 interface
DLMB
Data interface, local memory bus (block RAM only)
M_AXI_IP
Peripheral instruction interface, AXI4-Lite interface
ILMB
Instruction interface, local memory bus (block RAM only)
M0_AXIS..M15_AXIS
AXI4-Stream interface master direct connection interfaces
S0_AXIS..S15_AXIS
AXI4-Stream interface slave direct connection interfaces
M_AXI_DC
Data-side cache AXI4 interface
M_ACE_DC
Data-side cache AXI Coherency Extension (ACE) interface
M_AXI_IC
Instruction-side cache AXI4 interface
M_ACE_IC
Instruction-side cache AXI Coherency Extension (ACE) interface
S_AXI
Slave AXI4-Lite interface to access core trace and profiling registers
Core
Miscellaneous signals for clock, reset, interrupt, debug, and trace
Figure 1. Core Interfaces

Table 1. Summary of MicroBlaze V Core I/O
Signal Interface I/O Description
M_AXI_DP_AWID M_AXI_DP O Master Write address ID
M_AXI_DP_AWADDR M_AXI_DP O Master Write address
M_AXI_DP_AWLEN M_AXI_DP O Master Burst length
M_AXI_DP_AWSIZE M_AXI_DP O Master Burst size
M_AXI_DP_AWBURST M_AXI_DP O Master Burst type
M_AXI_DP_AWLOCK M_AXI_DP O Master Lock type
M_AXI_DP_AWCACHE M_AXI_DP O Master Cache type
M_AXI_DP_AWPROT M_AXI_DP O Master Protection type
M_AXI_DP_AWQOS M_AXI_DP O Master Quality of Service
M_AXI_DP_AWVALID M_AXI_DP O Master Write address valid
M_AXI_DP_AWREADY M_AXI_DP I Slave Write address ready
M_AXI_DP_WDATA M_AXI_DP O Master Write data
M_AXI_DP_WSTRB M_AXI_DP O Master Write strobes
M_AXI_DP_WLAST M_AXI_DP O Master Write last
M_AXI_DP_WVALID M_AXI_DP O Master Write valid
M_AXI_DP_WREADY M_AXI_DP I Slave Write ready
M_AXI_DP_BID M_AXI_DP I Slave Response ID
M_AXI_DP_BRESP M_AXI_DP I Slave Write response
M_AXI_DP_BVALID M_AXI_DP I Slave Write response valid
M_AXI_DP_BREADY M_AXI_DP O Master Response ready
M_AXI_DP_ARID M_AXI_DP O Master Read address ID
M_AXI_DP_ARADDR M_AXI_DP O Master Read address
M_AXI_DP_ARLEN M_AXI_DP O Master Burst length
M_AXI_DP_ARSIZE M_AXI_DP O Master Burst size
M_AXI_DP_ARBURST M_AXI_DP O Master Burst type
M_AXI_DP_ARLOCK M_AXI_DP O Master Lock type
M_AXI_DP_ARCACHE M_AXI_DP O Master Cache type
M_AXI_DP_ARPROT M_AXI_DP O Master Protection type
M_AXI_DP_ARQOS M_AXI_DP O Master Quality of Service
M_AXI_DP_ARVALID M_AXI_DP O Master Read address valid
M_AXI_DP_ARREADY M_AXI_DP I Slave Read address ready
M_AXI_DP_RID M_AXI_DP I Slave Read ID tag
M_AXI_DP_RDATA M_AXI_DP I Slave Read data
M_AXI_DP_RRESP M_AXI_DP I Slave Read response
M_AXI_DP_RLAST M_AXI_DP I Slave Read last
M_AXI_DP_RVALID M_AXI_DP I Slave Read valid
M_AXI_DP_RREADY M_AXI_DP O Master Read ready
M_AXI_IP_AWID M_AXI_IP O Master Write address ID
M_AXI_IP_AWADDR M_AXI_IP O Master Write address
M_AXI_IP_AWLEN M_AXI_IP O Master Burst length
M_AXI_IP_AWSIZE M_AXI_IP O Master Burst size
M_AXI_IP_AWBURST M_AXI_IP O Master Burst type
M_AXI_IP_AWLOCK M_AXI_IP O Master Lock type
M_AXI_IP_AWCACHE M_AXI_IP O Master Cache type
M_AXI_IP_AWPROT M_AXI_IP O Master Protection type
M_AXI_IP_AWQOS M_AXI_IP O Master Quality of Service
M_AXI_IP_AWVALID M_AXI_IP O Master Write address valid
M_AXI_IP_AWREADY M_AXI_IP I Slave Write address ready
M_AXI_IP_WDATA M_AXI_IP O Master Write data
M_AXI_IP_WSTRB M_AXI_IP O Master Write strobes
M_AXI_IP_WLAST M_AXI_IP O Master Write last
M_AXI_IP_WVALID M_AXI_IP O Master Write valid
M_AXI_IP_WREADY M_AXI_IP I Slave Write ready
M_AXI_IP_BID M_AXI_IP I Slave Response ID
M_AXI_IP_BRESP M_AXI_IP I Slave Write response
M_AXI_IP_BVALID M_AXI_IP I Slave Write response valid
M_AXI_IP_BREADY M_AXI_IP O Master Response ready
M_AXI_IP_ARID M_AXI_IP O Master Read address ID
M_AXI_IP_ARADDR M_AXI_IP O Master Read address
M_AXI_IP_ARLEN M_AXI_IP O Master Burst length
M_AXI_IP_ARSIZE M_AXI_IP O Master Burst size
M_AXI_IP_ARBURST M_AXI_IP O Master Burst type
M_AXI_IP_ARLOCK M_AXI_IP O Master Lock type
M_AXI_IP_ARCACHE M_AXI_IP O Master Cache type
M_AXI_IP_ARPROT M_AXI_IP O Master Protection type
M_AXI_IP_ARQOS M_AXI_IP O Master Quality of Service
M_AXI_IP_ARVALID M_AXI_IP O Master Read address valid
M_AXI_IP_ARREADY M_AXI_IP I Slave Read address ready
M_AXI_IP_RID M_AXI_IP I Slave Read ID tag
M_AXI_IP_RDATA M_AXI_IP I Slave Read data
M_AXI_IP_RRESP M_AXI_IP I Slave Read response
M_AXI_IP_RLAST M_AXI_IP I Slave Read last
M_AXI_IP_RVALID M_AXI_IP I Slave Read valid
M_AXI_IP_RREADY M_AXI_IP O Master Read ready
M_AXI_DC_AWADDR M_AXI_DC O Master Write address
M_AXI_DC_AWLEN M_AXI_DC O Master Burst length
M_AXI_DC_AWSIZE M_AXI_DC O Master Burst size
M_AXI_DC_AWBURST M_AXI_DC O Master Burst type
M_AXI_DC_AWLOCK M_AXI_DC O Master Lock type
M_AXI_DC_AWCACHE M_AXI_DC O Master Cache type
M_AXI_DC_AWPROT M_AXI_DC O Master Protection type
M_AXI_DC_AWQOS M_AXI_DC O Master Quality of Service
M_AXI_DC_AWVALID M_AXI_DC O Master Write address valid
M_AXI_DC_AWREADY M_AXI_DC I Slave Write address ready
M_AXI_DC_AWUSER M_AXI_DC O Master Write address user signals
M_AXI_DC_AWDOMAIN M_ACE_DC O Master Write address domain
M_AXI_DC_AWSNOOP M_ACE_DC O Master Write address snoop
M_AXI_DC_AWBAR M_ACE_DC O Master Write address barrier
M_AXI_DC_WDATA M_AXI_DC O Master Write data
M_AXI_DC_WSTRB M_AXI_DC O Master Write strobes
M_AXI_DC_WLAST M_AXI_DC O Master Write last
M_AXI_DC_WVALID M_AXI_DC O Master Write valid
M_AXI_DC_WREADY M_AXI_DC I Slave Write ready
M_AXI_DC_WUSER M_AXI_DC O Master Write user signals
M_AXI_DC_BRESP M_AXI_DC I Slave Write response
M_AXI_DC_BID M_AXI_DC I Slave Response ID
M_AXI_DC_BVALID M_AXI_DC I Slave Write response valid
M_AXI_DC_BREADY M_AXI_DC O Master Response ready
M_AXI_DC_BUSER M_AXI_DC I Slave Write response user signals
M_AXI_DC_WACK M_ACE_DC O Slave Write acknowledge
M_AXI_DC_ARID M_AXI_DC O Master Read address ID
M_AXI_DC_ARADDR M_AXI_DC O Master Read address
M_AXI_DC_ARLEN M_AXI_DC O Master Burst length
M_AXI_DC_ARSIZE M_AXI_DC O Master Burst size
M_AXI_DC_ARBURST M_AXI_DC O Master Burst type
M_AXI_DC_ARLOCK M_AXI_DC O Master Lock type
M_AXI_DC_ARCACHE M_AXI_DC O Master Cache type
M_AXI_DC_ARPROT M_AXI_DC O Master Protection type
M_AXI_DC_ARQOS M_AXI_DC O Master Quality of Service
M_AXI_DC_ARVALID M_AXI_DC O Master Read address valid
M_AXI_DC_ARREADY M_AXI_DC I Slave Read address ready
M_AXI_DC_ARUSER M_AXI_DC O Master Read address user signals
M_AXI_DC_ARDOMAIN M_ACE_DC O Master Read address domain
M_AXI_DC_ARSNOOP M_ACE_DC O Master Read address snoop
M_AXI_DC_ARBAR M_ACE_DC O Master Read address barrier
M_AXI_DC_RID M_AXI_DC I Slave Read ID tag
M_AXI_DC_RDATA M_AXI_DC I Slave Read data
M_AXI_DC_RRESP M_AXI_DC I Slave Read response
M_AXI_DC_RLAST M_AXI_DC I Slave Read last
M_AXI_DC_RVALID M_AXI_DC I Slave Read valid
M_AXI_DC_RREADY M_AXI_DC O Master Read ready
M_AXI_DC_RUSER M_AXI_DC I Slave Read user signals
M_AXI_DC_RACK M_ACE_DC O Master Read acknowledge
M_AXI_DC_ACVALID M_ACE_DC I Slave Snoop address valid
M_AXI_DC_ACADDR M_ACE_DC I Slave Snoop address
M_AXI_DC_ACSNOOP M_ACE_DC I Slave Snoop address snoop
M_AXI_DC_ACPROT M_ACE_DC I Slave Snoop address protection type
M_AXI_DC_ACREADY M_ACE_DC O Master Snoop ready
M_AXI_DC_CRREADY M_ACE_DC I Slave Snoop response ready
M_AXI_DC_CRVALID M_ACE_DC O Master Snoop response valid
M_AXI_DC_CRRESP M_ACE_DC O Master Snoop response
M_AXI_DC_CDVALID M_ACE_DC O Master Snoop data valid
M_AXI_DC_CDREADY M_ACE_DC I Slave Snoop data ready
M_AXI_DC_CDDATA M_ACE_DC O Master Snoop data
M_AXI_DC_CDLAST M_ACE_DC O Master Snoop data last
M_AXI_IC_AWID M_AXI_IC O Master Write address ID
M_AXI_IC_AWADDR M_AXI_IC O Master Write address
M_AXI_IC_AWLEN M_AXI_IC O Master Burst length
M_AXI_IC_AWSIZE M_AXI_IC O Master Burst size
M_AXI_IC_AWBURST M_AXI_IC O Master Burst type
M_AXI_IC_AWLOCK M_AXI_IC O Master Lock type
M_AXI_IC_AWCACHE M_AXI_IC O Master Cache type
M_AXI_IC_AWPROT M_AXI_IC O Master Protection type
M_AXI_IC_AWQOS M_AXI_IC O Master Quality of Service
M_AXI_IC_AWVALID M_AXI_IC O Master Write address valid
M_AXI_IC_AWREADY M_AXI_IC I Slave Write address ready
M_AXI_IC_AWUSER M_AXI_IC O Master Write address user signals
M_AXI_IC_AWDOMAIN M_ACE_IC O Master Write address domain
M_AXI_IC_AWSNOOP M_ACE_IC O Master Write address snoop
M_AXI_IC_AWBAR M_ACE_IC O Master Write address barrier
M_AXI_IC_WDATA M_AXI_IC O Master Write data
M_AXI_IC_WSTRB M_AXI_IC O Master Write strobes
M_AXI_IC_WLAST M_AXI_IC O Master Write last
M_AXI_IC_WVALID M_AXI_IC O Master Write valid
M_AXI_IC_WREADY M_AXI_IC I Slave Write ready
M_AXI_IC_WUSER M_AXI_IC O Master Write user signals
M_AXI_IC_BID M_AXI_IC I Slave Response ID
M_AXI_IC_BRESP M_AXI_IC I Slave Write response
M_AXI_IC_BVALID M_AXI_IC I Slave Write response valid
M_AXI_IC_BREADY M_AXI_IC O Master Response ready
M_AXI_IC_BUSER M_AXI_IC I Slave Write response user signals
M_AXI_IC_WACK M_ACE_IC O Slave Write acknowledge
M_AXI_IC_ARID M_AXI_IC O Master Read address ID
M_AXI_IC_ARADDR M_AXI_IC O Master Read address
M_AXI_IC_ARLEN M_AXI_IC O Master Burst length
M_AXI_IC_ARSIZE M_AXI_IC O Master Burst size
M_AXI_IC_ARBURST M_AXI_IC O Master Burst type
M_AXI_IC_ARLOCK M_AXI_IC O Master Lock type
M_AXI_IC_ARCACHE M_AXI_IC O Master Cache type
M_AXI_IC_ARPROT M_AXI_IC O Master Protection type
M_AXI_IC_ARQOS M_AXI_IC O Master Quality of Service
M_AXI_IC_ARVALID M_AXI_IC O Master Read address valid
M_AXI_IC_ARREADY M_AXI_IC I Slave Read address ready
M_AXI_IC_ARUSER M_AXI_IC O Master Read address user signals
M_AXI_IC_ARDOMAIN M_ACE_IC O Master Read address domain
M_AXI_IC_ARSNOOP M_ACE_IC O Master Read address snoop
M_AXI_IC_ARBAR M_ACE_IC O Master Read address barrier
M_AXI_IC_RID M_AXI_IC I Slave Read ID tag
M_AXI_IC_RDATA M_AXI_IC I Slave Read data
M_AXI_IC_RRESP M_AXI_IC I Slave Read response
M_AXI_IC_RLAST M_AXI_IC I Slave Read last
M_AXI_IC_RVALID M_AXI_IC I Slave Read valid
M_AXI_IC_RREADY M_AXI_IC O Master Read ready
M_AXI_IC_RUSER M_AXI_IC I Slave Read user signals
M_AXI_IC_RACK M_ACE_IC O Master Read acknowledge
M_AXI_IC_ACVALID M_ACE_IC I Slave Snoop address valid
M_AXI_IC_ACADDR M_ACE_IC I Slave Snoop address
M_AXI_IC_ACSNOOP M_ACE_IC I Slave Snoop address snoop
M_AXI_IC_ACPROT M_ACE_IC I Slave Snoop address protection type
M_AXI_IC_ACREADY M_ACE_IC O Master Snoop ready
M_AXI_IC_CRREADY M_ACE_IC I Slave Snoop response ready
M_AXI_IC_CRVALID M_ACE_IC O Master Snoop response valid
M_AXI_IC_CRRESP M_ACE_IC O Master Snoop response
M_AXI_IC_CDVALID M_ACE_IC O Master Snoop data valid
M_AXI_IC_CDREADY M_ACE_IC I Slave Snoop data ready
M_AXI_IC_CDDATA M_ACE_IC O Master Snoop data
M_AXI_IC_CDLAST M_ACE_IC O Master Snoop data last
Data_Addr[0:N-1] DLMB O Data interface LMB address bus, N = 32 - 64
Data_Prot[0:1] DLMB O Optional data interface LMB protection
Byte_Enable[0:3] DLMB O Data interface LMB byte enables
Data_Write[0:31] DLMB O Data interface LMB write data bus
D_AS DLMB O Data interface LMB address strobe
Read_Strobe DLMB O Data interface LMB read strobe
Write_Strobe DLMB O Data interface LMB write strobe
Data_Read[0:31] DLMB I Data interface LMB read data bus
DReady DLMB I Data interface LMB data ready
DWait DLMB I Data interface LMB data wait
DCE DLMB I Data interface LMB correctable error
DUE DLMB I Data interface LMB uncorrectable error
Instr_Addr[0:N-1] ILMB O Instruction interface LMB address bus, N = 32 - 64
Instr_Prot[0:1] ILMB O Optional instruction interface LMB protection
I_AS ILMB O Instruction interface LMB address strobe
IFetch ILMB O Instruction interface LMB instruction fetch
Instr[0:31] ILMB I Instruction interface LMB read data bus
IReady ILMB I Instruction interface LMB data ready
IWait ILMB I Instruction interface LMB data wait
ICE ILMB I Instruction interface LMB correctable error
IUE ILMB I Instruction interface LMB uncorrectable error
Mn_AXIS_TLAST

M0_AXIS..

M15_AXIS

 O Master interface output AXI4 channels write last
Mn_AXIS_TDATA

M0_AXIS..

M15_AXIS

 O Master interface output AXI4 channels write data
Mn_AXIS_TVALID

M0_AXIS..

M15_AXIS

 O Master interface output AXI4 channels write valid
Mn_AXIS_TREADY

M0_AXIS..

M15_AXIS

 I Master interface input AXI4 channels write ready
Sn_AXIS_TLAST

S0_AXIS..

S15_AXIS

 I Slave interface input AXI4 channels write last
Sn_AXIS_TDATA

S0_AXIS..

S15_AXIS

 I Slave interface input AXI4 channels write data
Sn_AXIS_TVALID

S0_AXIS..

S15_AXIS

 I Slave interface input AXI4 channels write valid
Sn_AXIS_TREADY

S0_AXIS..

S15_AXIS

 O Slave interface output AXI4 channels write ready
S_AXI_AWADDR S_AXI I Slave Write address
S_AXI_AWVALID S_AXI I Slaver Write address valid
S_AXI_AWREADY S_AXI O Master Write address ready
S_AXI_WDATA S_AXI I Slave Write data
S_AXI_WVALID S_AXI I Slave Write valid
S_AXI_WREADY S_AXI O Master Write ready
S_AXI_BRESP S_AXI O Master Write response
S_AXI_BVALID S_AXI O Master Write response valid
S_AXI_BREADY S_AXI I Slave Response ready
S_AXI_ARADDR S_AXI I Slave Read address
S_AXI_ARVALID S_AXI I Slave Read address valid
S_AXI_ARREADY S_AXI O Master Read address ready
S_AXI_RDATA S_AXI O Master Read data
S_AXI_RRESP S_AXI O Master Read response
S_AXI_RVALID S_AXI O Master Read valid
S_AXI_RREADY S_AXI I Slave Read ready
Interrupt Core I Interrupt. The signal is synchronized to Clk if the parameter C_ASYNC_INTERRUPT is set.
Interrupt_Address 1 Core I Interrupt vector address
Interrupt_Ack 1 Core O Interrupt acknowledge
Reset Core I Core reset, active-High. Must be asserted one Clk clock cycle, but it is recommended to keep it asserted for at least 16 clock cycles.
Reset_Mode[0:1] 3 Core I Reset mode. Sampled when reset is active.
Clk Core I Clock 2
Ext_BRK 3 Core I Break signal, implemented as RISC-V platform interrupt
Ext_NM_BRK 3 Core I Non-maskable break, implemented as RISC-V non-maskable interrupt
Halted 3 Core O Pipeline is halted, either using the Debug interface, by setting Dbg_Stop, or by setting Reset_Mode[0:1] to 10.
Dbg_Stop 3 Core I Unconditionally force pipeline to halt as soon as possible. Rising-edge detected pulse that must be held for at least one Clk clock cycle. The signal only has any effect when C_DEBUG_ENABLED is greater than 0.
Sleep 3 Core O MicroBlaze V is in sleep mode after executing a wfi instruction or by setting Reset_Mode[0:1] to 10. All external accesses are completed, and the pipeline is halted. Set when mwfi = 1 or C_USE_SLEEP = 1.
Hibernate 3 Core O MicroBlaze V is in sleep mode after executing a wfi instruction or by setting Reset_Mode[0:1] to 10. All external accesses are completed, and the pipeline is halted. Set when mwfi = 2 or C_USE_SLEEP = 2.
Suspend 3 Core O MicroBlaze V is in sleep mode after executing a wfi instruction or by setting Reset_Mode[0:1] to 10. All external accesses are completed, and the pipeline is halted. Set when mwfi = 4 or C_USE_SLEEP = 4.
Wakeup[0:1] 3 Core I Wake MicroBlaze V from sleep mode when either or both bits are set to 1. Ignored if not in sleep mode. The signals are individually synchronized to Clk according to the parameter C_ASYNC_WAKEUP[0:1].
Dbg_Wakeup 3 Core O Debug request that external logic wakes MicroBlaze V from sleep mode with the Wakeup signal, to allow debug access. Synchronous to Dbg_Update.
Pause 3 Core I When this signal is set, the MicroBlaze V pipeline is paused after completing all ongoing bus accesses, and the Pause_Ack signal is set. When this signal is cleared again MicroBlaze V continues normal execution where it was paused.
Pause_Ack 3 Core O MicroBlaze V is in pause mode after the Pause input signal has been set.
Dbg_Continue 3 Core O Debug request that external logic clears the Pause signal, to allow debug access.
Non_Secure[0:3] 3 Core I Determines whether AXI accesses are non-secure or secure. The default value is binary 0000, setting all interfaces to be secure.

Bit 0 = M_AXI_DP

Bit 1 = M_AXI_IP

Bit 2 = M_AXI_DC

Bit 3 = M_AXI_IC

Dbg_Inhibit Core I Activates secure debug inhibit functionality according to the PMP debug inhibit parameter.
Lockstep_... Core IO Lockstep signals for high integrity applications
Dbg_... Core IO Debug signals from MDM V
Trace_... Core O Trace signals for real time hardware analysis
  1. Only used with C_USE_INTERRUPT = 2, for low-latency interrupt support.
  2. MicroBlaze V is a synchronous design clocked with the Clk signal, except for serial hardware debug logic, which is clocked with the Dbg_Clk signal. If serial hardware debug logic is not used, there is no minimum frequency limit for Clk. However, if serial hardware debug logic is used, there are signals transferred between the two clock regions. In this case Clk must have a higher frequency than Dbg_Clk.
  3. Only visible when C_ENABLE_DISCRETE_PORTS = 1.
Table 2. Effect of Reset Mode Inputs
Reset_Mode[0:1] Description
00 MicroBlaze V starts executing at the reset vector, defined by C_BASE_VECTORS. This is the nominal default behavior.
01 MicroBlaze V immediately enters sleep mode without performing any bus access, as if a wfi instruction has been executed. The sleep/hibernate/suspend output is set to 1. When any of the Wakeup[0:1] signals is set, MicroBlaze V starts executing at the reset vector, defined by C_BASE_VECTORS.

This functionality can be useful in a multiprocessor configuration.
10 If C_DEBUG_ENABLED is 0, the behavior is the same as if Reset_Mode[0:1] = 00.

If C_DEBUG_ENABLED is greater than 0, MicroBlaze V immediately enters debug halt without performing any bus access, the DCSR cause is set to 5, and the Halted output is set to 1. When execution is continued via the debug interface, MicroBlaze V starts executing at the reset vector, defined by C_BASE_VECTORS.
11 Reserved

In general, MicroBlaze V signals are synchronous to the Clk input signal. However, there are some exceptions controlled by parameters as described in the following table.

Table 3. Parameter Controlled Asynchronous Signals
Signal Parameter Default Description
Interrupt C_ASYNC_INTERRUPT Tool controlled Parameter set from connected signal
Reset C_NUM_SYNC_FF_CLK 2 Parameter can be manually set to 0 for synchronous reset
Wakeup[0:1]

C_ASYNC_WAKEUP

C_NUM_SYNC_FF_CLK

Tool controlled

2

 Set from connected signals. Can be manually set to 0 to override tool.
Dbg_Wakeup C_DEBUG_INTERFACE 0 (serial) 0: Clocked by Dbg_Update.

1: Clocked by DEBUG_ACLK, synchronous to Clk.