MicroBlaze V is implemented with a Harvard memory architecture; instruction and data accesses are done in separate address spaces.
With the 32-bit implementation (RV32), the address space has a 32-bit virtual address range (that is, handles up to 4 GB), and a 34-bit physical address range (16 GB) when using the Sv32 page-based virtual memory system.
With the 64-bit implementation (RV64), the address space has a default 32-bit physical address range, which can be extended up to a 64-bit range (that is, handles from 4 GB to 16 EB). When physical memory protection (PMP) is enabled, the maximum address range is limited to 56 bits (64 PB). When using the Sv39 page-based virtual memory system, the virtual address range is 39 bits (512 GB) and the physical address range is 56 bits (64 PB).
The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory. This is necessary for software debugging.
Both instruction and data interfaces of MicroBlaze V are 32 bits wide and use little endian format. MicroBlaze V supports word, half word, and byte accesses to data memory.
Data accesses must be aligned (word accesses must be on word boundaries,
half word accesses on half word boundaries), unless software supports misaligned
exception handling. All instruction accesses must be word aligned, unless compressed
instructions are enabled (C_USE_COMPRESSION > 0), in
which case accesses are half-word aligned.
MicroBlaze V prefetches instructions to improve performance, using the instruction prefetch buffer and (if enabled) instruction cache streams. To avoid attempts to prefetch instructions beyond the end of physical memory, which might cause an instruction access error or a processor stall, instructions must not be located too close to the end of physical memory. The instruction prefetch buffer requires 16 bytes margin, and using instruction cache streams adds two additional cache lines (32, 64, or 128 bytes).
MicroBlaze V does not separate data accesses to I/O and memory (it uses memory-mapped I/O). The processor has up to three interfaces for memory accesses:
- Local memory bus (LMB)
- Advanced eXtensible Interface (AXI4) for peripheral access
- Advanced eXtensible Interface (AXI4) or AXI Coherency Extension (ACE) for cache access
The LMB memory address range must not overlap with AXI4 ranges.
MicroBlaze V has a single cycle latency for
accesses to local memory (LMB) and for cache read hits, except with C_OPTIMIZATION set to 1 (area), when data side accesses and
data cache read hits require two clock cycles, and with error correction codes (ECCs)
when byte writes and half word writes to LMB normally require one additional clock
cycle.
The data cache write latency depends on C_DCACHE_USE_WRITEBACK. When C_DCACHE_USE_WRITEBACK is set to 1, the write latency normally is one
cycle (more if the cache needs to do memory accesses). When C_DCACHE_USE_WRITEBACK is cleared to 0, the write latency normally is two
cycles (more if the posted-write buffer in the memory controller is full).
The MicroBlaze V instruction and data caches can be configured to use 4, 8, or 16 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns. However, for software with a more random access pattern the performance can instead decrease for a given cache size. This is caused by a reduced cache hit rate due to fewer available cache lines.
For details on the different memory interfaces, see MicroBlaze V Signal Interface Description.