The mstream register is a read/write custom CSR with the number 0x7C0. It
holds information related to executed AXI4-Stream
custom instructions. It only exists when AXI4-Stream custom instructions are enabled (C_FSL_LINKS > 0).
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 1 | FSL |
GET or GETD custom instruction TLAST control bit mismatch. A mismatch occurs when the custom instruction expects TLAST to be set (the instruction 'c' bit is set) and it is not, or vice versa. This bit is sticky, meaning that it is set by the first GET or GETD custom instruction with a mismatch, and remains set until cleared by software. |
0 |
| 0 | C | A non-blocking GET or GETD custom instruction sets this bit to 1 if no
data is available and to 0 if valid data is read. A non-blocking PUT or PUTD custom instruction sets this bit to 1 if data could not be written and to 0 if data is successfully written. This bit represents the result of the last executed non-blocking custom instruction. |
0 |