Machine Security Configuration Register (mseccfg) - 2025.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)

Document ID
UG1629
Release Date
2025-07-09
Version
2025.1 English

The mseccfg register is an optional read/write register that controls security features. It only exists when PMP is enabled (C_PMP_ENTRIES > 0) and PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) is enabled (C_PMP_ENHANCEMENTS > 0).

Figure 1. Machine Security Configuration Register
Table 1. Machine Security Configuration Register
Bits Name Description Reset Value
2 RLB Rule Locking Bypass 0
1 MMWP Machine Mode Whitelist Policy 0
0 MML Machine Mode Lockdown 0