The mnivec register is a custom optional read/write register that holds
non-maskable interrupt vector configuration, consisting of a vector base address
(BASE) with the two least significant bit set to zero. It only exists when the
"Smrnmi" Extension for Resumable Non-Maskable Interrupts is enabled (C_TRAP_ENHANCEMENT > 1).
Figure 1. Machine Non-Maskable Interrupt-Vector Base-Address Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 31:2 | BASE | Vector base address | (C_BASE_VECTORS + 8) / 4 |
| 1:0 | MODE | Read only zero | 00 |
The trap handler code must be aligned on a 32-bit word boundary.
With compressed instructions enabled (C_USE_COMPRESSION > 0), software must use an align attribute to
ensure this is the case.
With the RISC-V GCC compiler, this can be achieved with the following code:
/* Ensure alignment on a word boundary */
void non_maskable_interrupt_handler(void) __attribute__((aligned(4)));