Machine Interrupt Registers (mip and mie) - 2025.2 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2025-11-20
Version
2025.2 English

The mip register is a read-only register containing information on pending interrupts, while mie is the corresponding read/write register containing interrupt enable bits.

Figure 1. Machine External Break Pending (MEBP) and Machine External Interrupt Pending (MEIP)

Table 1. Machine Interrupt Pending Register
Bits Name Description Reset Value
16 MEBP Machine external break pending. Custom platform interrupt, using the external break input. Exists when the external break signal is enabled. Ext_Brk
11 MEIP Machine external interrupt pending. Exists when interrupts are enabled. Interrupt
9 SEIP Supervisor external interrupt pending. Exists when interrupts and supervisor mode are enabled. Interrupt
5 STIP Supervisor timer interrupt pending. Exists when the "Sstc" extension and supervisor mode are enabled. 0
Figure 2. Machine External Break Enable (MEBE) and Machine External Interrupt Enable (MEIE)

Table 2. Machine Interrupt Enable Register
Bits Name Description Reset Value
16 MEBE Machine external break enable. Custom platform interrupt, using the external break input. Exists when interrupts are enabled. 0
11 MEIE Machine external interrupt enable. Exists when interrupts are enabled. 0
9 SEIE Supervisor external interrupt enable. Exists when interrupts and supervisor mode are enabled. 0
5 STIE Supervisor timer interrupt enable. Exists when the "Sstc" extension and supervisor mode are enabled. 0