The misa CSR is a read-only register reporting the ISA supported by the processor.
Figure 1. Machine ISA Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 31:30 | MXL | XLEN = 32 (C_DATA_SIZE = 32) or XLEN = 64 (C_DATA_SIZE = 64) | 01 or 10 |
| 23 | X | Set to 1 if custom instructions are implemented (C_FSL_LINKS > 0) or C_ADDR_SIZE > 32 for RV32 | 0 or 1 |
| 20 | U | Set to 1 if user mode is implemented (C_USE_MMU = 1). | 0 or 1 |
| 18 | S | Set to 1 if supervisor mode is implemented (C_USE_MMU = 3). | |
| 12 | M | Set to 1 if multiplication and division (M-extension) are implemented (C_USE_MULDIV > 0). | 0 or 1 |
| 8 | I | RV32I or RV64I | 1 |
| 5 | F | Set to 1 if single-precision floating-point (F-extension) is implemented (C_USE_FPU > 0). | 0 or 1 |
| 3 | D | Set to 1 if double-precision floating-point (D-extension) is implemented (C_USE_FPU = 2). | 0 or 1 |
| 2 | C | Set to 1 if compressed instructions (C-extension) are implemented (C_USE_COMPRESSION > 0). | 0 or 1 |
| 1 | B | Set to 1 if the bit manipulation extension (B-extension) is implemented (C_USE_BITMAN_A = 1, C_USE_BITMAN_B = 1, C_USE_BITMAN_S = 1) | 0 or 1 |
| 0 | A | Set to 1 if atomic instructions (A-extension) is implemented (C_USE_ATOMIC > 0). | 0 or 1 |