The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses a minimum number of control signals and a simple protocol to ensure that local block RAM are accessed in a single clock cycle. LMB signals and definitions are shown in the following table. All LMB signals are active-High.
LMB provides an optional frequency optimized protocol for the 8-stage pipeline,
selected by setting the parameters C_DLMB_PROTOCOL = 1 for the data
interface and C_ILMB_PROTOCOL = 1 for the instruction interface. When
this protocol is used, all LMB input signals are delayed one clock cycle. This can
improve the maximum frequency, particularly when ECC is enabled.