Description
Loads a word (32 bits) from the word aligned memory location that results from the effective address formed by concatenating the contents of registers rs1 and rs1+1. The data is placed in register rd. The rs1 register number must be even. Use of a misaligned (odd-numbered) register is reserved.
A load address misaligned exception occurs when the effective address has any of the two least significant bits set.
A load access fault exception occurs in case of an unsuccessful Physical Memory Access (PMA) check, or in case of errors when reading data from memory.
A load page fault exception is caused by an unsuccessful virtual memory effective address translation.
Pseudocode
Addr ← (rs1 + 1) (rs1)
(rd) ← Mem(Addr)Registers Altered
rd, unless a trap occurs, in which case the register is unchanged
Latency
- One cycle with
C_OPTIMIZATION= 0, 2, 3 - Two cycles with
C_OPTIMIZATION= 1
Notes
- The instruction is only valid if MicroBlaze V is configured to use extended address with PMP disabled (C_ADDR_SIZE > 32, C_PMP_ENTRIES = 0) and with RV32I Base Integer Instruction Set (C_DATA_SIZE = 32).
- Instruction bits 20-24 and 26-28 are ignored when decoding the instruction.