Interface Parameters and Signals - 2025.1 English - UG1629

AXI4-Lite: Default.

AXI4: Used to allow exclusive access when C_M_AXI_DP_EXCLUSIVE_ACCESS is 1.

M_AXI_IC

M_ACE_IC

32: Default, single word accesses and burst accesses with C_ICACHE_LINE_LEN word busts used with AXI4 and ACE.

128: Used when C_ICACHE_DATA_WIDTH is set to 1 and C_ICACHE_LINE_LEN is set to 4 with AXI4. Only single accesses can occur.

256: Used when C_ICACHE_DATA_WIDTH is set to 1 and C_ICACHE_LINE_LEN is set to 8 with AXI4. Only single accesses can occur.

512: Used when C_ICACHE_DATA_WIDTH is set to 2, or when it is set to 1 and C_ICACHE_LINE_LEN is set to 16 with AXI4. Only single accesses can occur.

M_AXI_DC

M_ACE_DC

32: Default, single word accesses and burst accesses with C_DCACHE_LINE_LEN word busts used with AXI4 and ACE.

Write bursts are only used with AXI4 when C_DCACHE_USE_WRITEBACK is set to 1.

128: Used when C_DCACHE_DATA_WIDTH is set to 1 and C_DCACHE_LINE_LEN is set to 4 with AXI4. Only single accesses can occur.

256: Used when C_DCACHE_DATA_WIDTH is set to 1 and C_DCACHE_LINE_LEN is set to 8 with AXI4. Only single accesses can occur.

512: Used when C_DCACHE_DATA_WIDTH is set to 2, or when it is set to 1 and C_DCACHE_LINE_LEN is set to 16 with AXI4. Only single accesses can occur.

M_AXI_IC

M_ACE_IC

1: Default for 128-bit, 256-bit and 512-bit masters, a single outstanding read.

2: Default for 32-bit masters, 2 simultaneous outstanding reads.

8: Used for 32-bit masters when C_ICACHE_STREAMS is set to 1, allowing 8 simultaneous outstanding reads.

Can be set to 1, 2, or 8.

M_AXI_DC

M_ACE_DC

1: Default for 128-bit, 256-bit and 512-bit masters, a single outstanding read.

2: Default for 32-bit masters, two simultaneous outstanding reads.

Can be set to 1 or 2.

M_AXI_DC

M_ACE_DC

32: Default, 32 simultaneous outstanding writes.

Can be set to 1, 2, 4, 8, 16, or 32.

Access permission:

C_M_AXI_DP_ARCACHE

C_M_AXI_DP_AWCACHE

Memory type, AXI4 protocol:

Normal non-cacheable bufferable (0011)

C_M_AXI_DP_ARPROT

C_M_AXI_DP_AWPROT

Access permission, AXI4 and AXI4-Lite protocol:

• Unprivileged, secure data access (000) if input signal Non_Secure[0] = 0
• Unprivileged, non-secure data access (010) if input signal Non_Secure[0] = 1

C_M_AXI_DP_ARQOS

C_M_AXI_DP_AWQOS

Quality of service, AXI4 protocol:

• Priority 8 (1000)

Memory type:

• Write-back read and write-allocate (1111)

Memory type, normal access:

• Write-back read and write-allocate (1111)

Memory type, DVM access:

• Normal non-cacheable non-bufferable (0010)

Shareability domain:

• Inner shareable (01)

M_AXI_IC

M_ACE_IC

Access permission:

• Unprivileged, secure instruction access (100) if input signal Non_Secure[3] = 0
• Unprivileged, non-secure instruction access (110) if input signal Non_Secure[3] = 1

Quality of service:

• Priority 7 (0111)

Memory type, normal access:

• Write-back Read and Write-allocate (1111)

Memory Type, exclusive access:

• Normal non-cacheable non-bufferable (0010)

Memory type, normal and exclusive access:

• Write-back read and write-allocate (1111)

Memory type, DVM access:

• Normal non-cacheable non-bufferable (0010)

C_M_AXI_DC_ARDOMAIN

C_M_AXI_DC_AWDOMAIN

Shareability domain:

• Inner shareable (01)

M_AXI_DC

M_ACE_DC

Memory type, normal access:

• Write-back read and write-allocate (1111)

Memory type, exclusive access:

• Normal non-cacheable non-bufferable (0010)

C_M_AXI_DC_ARPROT

C_M_AXI_DC_AWPROT

Access permission:

• Unprivileged, secure data access (000) if input signal Non_Secure[2] = 0
• Unprivileged, non-secure data access (010) if input signal Non_Secure[2] = 1

Quality of service, read access:

• Priority 12 ((1100)

Quality of service, write access:

• Priority 8 (1000)