After reset is released, the instruction cache is initialized by hardware
invalidating all cache lines individually. The initialization requires C_ICACHE_BYTE_SIZE / (C_ICACHE_LINE_LEN * 4) clock cycles. While it is in progress, reads within
the cacheable range directly access memory, bypassing the cache. Any FENCE.I or CBO
instructions during initialization are ignored.
For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the M_AXI_IP or ILMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller requests the new instruction over the instruction AXI4 interface (M_AXI_IC), and waits for the memory controller to return the associated cache line.
When software executes FENCE.I, the processor invalidates all instruction-cache locations. In 3-, 4-, and 5-stage pipelines, execution continues while invalidation is in progress, and instruction fetches in cacheable regions bypass the instruction cache during this interval. In this case, additional FENCE.I instructions issued before invalidation completes have no effect.
C_ICACHE_DATA_WIDTH determines the bus
data width, either 32 bits, an entire cache line (128, 256, or 512 bits), or 512
bits.
When C_FAULT_TOLERANT is set to 1, a cache miss
also occurs if a parity error is detected in a tag or instruction block RAM.
The instruction cache issues burst accesses for the AXI4 interface when 32-bit data width is used, otherwise single accesses are used.