When the Pause input signal is set to one and
MicroBlaze V has completed all external accesses, the
pipeline is halted and the Pause_Ack output signal is
set. This indicates to external hardware that it is safe to perform actions such as
stopping the clock, resetting the processor or other IP cores. To continue from pause,
the input signal Pause must be cleared to zero. In this
case, MicroBlaze V continues instruction execution where
it was previously paused.
The Dbg_Continue output signal from MicroBlaze V indicates that the debugger requests the
processor to continue from pause. External hardware must handle this signal and clear
pause after performing any other necessary hardware actions such as starting the
clock.
After external hardware has set or cleared Pause, it is recommended to wait until Pause_Ack is set or cleared before Pause
is changed again, to avoid any issues due to incorrectly detected pause acknowledge.
All signals used for hardware control (Pause, Pause_Ack, and Dbg_Continue) are synchronous to the MicroBlaze V clock.
The following block diagram illustrates how to use the pause functionality to
halt the processor and how to implement clock control. In this example, Pause is an external hardware signal that pauses processor
execution and stops the clock. When Pause is cleared to
zero, the clock is enabled and execution resumes. This example assumes that the external
logic monitors Dbg_Continue, and clears Pause to allow debugging.
