External Interrupt - 2025.2 English - UG1629

MicroBlaze V supports one external interrupt source (connected to the Interrupt input port). The processor only reacts to interrupts if:

• Both the global interrupt enable bit MIE in mstatus and the external interrupt enable bit MEIE in mie are set to 1, or
• Both the supervisor global interrupt enable bit SIE in sstatus and the supervisor external interrupt enable bit SEIE in sie are set to 1 when supervisor mode is enabled.

On an interrupt, the instruction in the execution stage completes while the instruction in the decode stage is replaced by a branch to the trap-vector base-address in mtvec or stvec, or with low-latency interrupt mode, the address supplied by the Interrupt Controller.

The interrupt return address (the PC associated with the instruction in the decode stage at the time of the interrupt) is automatically loaded into mepc or sepc. In addition, the processor also disables future interrupts by clearing the global interrupt enable bit MIE or SIE in mstatus to 0. The MIE or SIE bit is automatically set again when executing the MRET or SRET instruction.

By using the parameter C_INTERRUPT_IS_EDGE, the external interrupt can either be set to level-sensitive or edge-triggered:

• When using level-sensitive interrupts, the Interrupt input must remain set until MicroBlaze V has taken the interrupt, and jumped to the trap vector. The software must acknowledge the interrupt at the source to clear it before returning from the interrupt handler. If not, the interrupt is taken again, as soon as interrupts are enabled when returning from the trap handler.
• When using edge-triggered interrupts, MicroBlaze V detects and latches the Interrupt input edge, which means that the input only needs to be asserted one clock cycle. The interrupt input can remain asserted but must be deasserted at least one clock cycle before a new interrupt can be detected. The latching of an edge-triggered interrupt is independent of the global interrupt enable bit MIE or SIE. If an interrupt occurs while the bit is 0, it is immediately serviced when the bit is set to 1 (and the external interrupt enable bit MEIE or SEIE is set to 1). The MEIP bit in MIP and SEIP bit in SIP is set when the interrupt is latched and cleared when returning from the trap handler with the MRET or SRET instruction.

With periodic interrupt sources, such as the FIT Timer IP core, that do not have a method to clear the interrupt from the software, it is recommended to use edge-triggered interrupts.