Exception Causes - 2025.1 English - UG1629

MicroBlaze V Processor Reference Guide (UG1629)
Document ID
UG1629
Release Date
2025-07-09
Version
2025.1 English
Instruction address misaligned
When compressed instructions are not enabled, the misaligned exception is caused by an instruction access where the address to the instruction bus has the second least significant bit set.

When compressed instructions are enabled, the exception cannot occur.

Instruction access fault
The instruction access fault exception is caused by errors when reading data from memory.
  • The instruction peripheral AXI4 interface (M_AXI_IP) exception is caused by an error response on M_AXI_IP_RRESP.
  • The instruction side local memory (ILMB) can only cause an instruction access fault when an uncorrectable error occurs in the LMB memory (as indicated by the IUE signal), or when C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the ICE signal.
Illegal instruction
When complete illegal instruction decoding is enabled (C_ILL_INSTR_EXCEPTION = 2) the illegal instruction exception occurs for all unimplemented or undefined instructions, including access to all unimplemented or undefined control and status registers. Decoding takes into account which extensions and modes are enabled.

When basic illegal instruction decoding is enabled (C_ILL_INSTR_EXCEPTION = 1) the illegal instruction exception only occurs for unimplemented opcodes. Decoding takes into account which extensions are enabled.

Otherwise, the illegal instruction exception cannot occur.

Load address misaligned
The misaligned exception is caused by a word access where the address to the data bus has any of the two least significant bits set, or a half word access with the least significant bit set.
For the 64-bit implementation (RV64), a misaligned exception is also caused by a double access where the address to the data bus has any of the three least significant bits set.
Load access fault
The load access fault exception is caused by errors when reading data from memory. This can also occur for a virtual memory translation page table access.
  • The data peripheral AXI4 interface (M_AXI_DP) exception is caused by an error response on M_AXI_DP_RRESP or an OKAY response in case of an exclusive access using a load-reserved (LR) or atomic (AMO) instruction load.
  • The data cache AXI4 interface (M_AXI_DC) exception is caused by an OKAY response on M_AXI_DC_RRESP in case of an exclusive access using a load-reserved (LR) or atomic (AMO) instruction load. The exception can only occur when an exclusive access using LR is performed. In all other cases the response is ignored.
  • The data side local memory (DLMB) can only cause a load access fault exception when either an uncorrectable error occurs in the LMB memory, as indicated by the DUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the DCE signal.
The load access fault exception is also caused by an unsuccessful physical memory protection (PMP) check.
Store/AMO address misaligned
The misaligned exception is caused by a word access where the address to the data bus has any of the two least significant bits set, or a half word access with the least significant bit set.
For the 64-bit implementation (RV64), a misaligned exception is also caused by a double access where the address to the data bus has any of the three least significant bits set.
Store/AMO access fault
The store/AMO access fault exception is caused by errors when writing data to memory, or when an AMO instruction accesses memory.
  • The data peripheral AXI4 interface (M_AXI_DP) exception is caused by an error response on M_AXI_DP_BRESP.
  • The data cache AXI4 interface (M_AXI_DC) exception is caused by an error response on M_AXI_DC_BRESP. The exception can only occur when an exclusive access using SC is performed. In all other cases, the response is ignored.
  • The data side local memory (DLMB) can only cause a load access fault exception when either an uncorrectable error occurs in the LMB memory, as indicated by the DUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the DCE signal. An error can only occur for byte and half word write accesses.

The store/AMO access fault exception is also caused by an unsuccessful physical memory protection (PMP) check.

Instruction page fault
The instruction page fault is caused by an unsuccessful virtual memory instruction address translation.
Load page fault
The load page fault is caused by an unsuccessful virtual memory data address translation for a load instruction.
Store/AMO page fault
The store/AMO page fault is caused by an unsuccessful virtual memory data address translation for a store or AMO instruction.
AXI4-Stream exception
The AXI4-Stream exception is caused by a GET or GETD custom instruction TLAST control bit mismatch when the instruction 'e' bit is set. A mismatch either occurs when the custom instruction expects TLAST to be set (the instruction 'c' bit is set) and it is not, or vice versa.

Imprecise Exceptions

Normally all exceptions in MicroBlaze V are precise, meaning that any instructions in the pipeline after the instruction causing an exception are invalidated, and have no effect.

When C_IMPRECISE_EXCEPTIONS is set to 1 an Instruction Access Fault, Load Access Fault, or Store/AMO Access Fault exception is not precise, meaning that a subsequent memory access instruction in the pipeline might be executed. If this behavior is acceptable, the maximum frequency or performance can be improved by setting this parameter to 1.

When using the 3-stage, 4-stage or 5-stage pipelines (C_OPTIMIZATION ≠ 2 ) imprecise exceptions can only be caused by ECC errors in LMB memory. The advantage of enabling imprecise exceptions is improved maximum frequency.

When using the 8-stage pipeline (C_OPTIMIZATION = 2)imprecise exceptions can be caused by any erroneous memory access. The advantage of enabling imprecise exceptions is improved performance.

Equivalent Pseudocode

if C_USE_MMU > 1 and medeleg(exception cause) = 1
   sepc ← PC
   PC ← stvec
   scause ← exception cause
   if privilege mode = 00
      sstatus.sie ← 0
   else
      sstatus.spp ← 1
   stval ← exception specific value
else
   mepc ← PC
   PC ← mtvec
   mcause ← exception cause
   mstatus.mpie ← mstatus.mie
   mstatus.mie ← 0
   if C_USE_MMU > 0
      mstatus.mpp ← privilege mode
   else
      mstatus.mpp ← 11
   mtval ← exception specific value
Reservation ← 0

The actual scause, stval, mcause, and mtval values depend on the exception. See the description of the registers for details.