Data Cache Operation - Data Cache Operation - 2026.1 English - UG1629

After reset is released, the data cache is initialized by hardware by invalidating all cache lines individually. The initialization requires C_DCACHE_BYTE_SIZE / (C_DCACHE_LINE_LEN * 4) clock cycles. While it is in progress, accesses within the cacheable range directly access memory, bypassing the cache. Any FENCE.I or CBO instructions issued before initialization completes are ignored.

The caching policy used by the MicroBlaze V data cache, write-back or write-through, is determined by the parameter C_DCACHE_USE_WRITEBACK. When this parameter is set, a write-back protocol is implemented; otherwise, write-through is implemented.

With the write-back protocol, a store to an address within the cacheable range always updates the cached data. If the target address word is in the cache (a cache hit), the store completes immediately. If the target address word is not in the cache (a cache miss), and the location in the cache contains data that has not yet been written to memory (the cache location is dirty), the old data is written over the data AXI4 interface (M_AXI_DC) to external memory before updating the cache with the new data. If only a single word needs to be written, a single word write is used. Otherwise, a burst write is used. If the cache location is not dirty, the store completes immediately. For byte or half word stores, in case of a cache miss, the address is first requested over the data AXI4 interface, using a burst read. A word store only updates the cache. For byte or half word stores, the processor pipeline stalls until the cache line associated with the target address is returned from the external memory controller.

With the write-through protocol, a store to an address within the cacheable range generates an equivalent byte, half word, or word write over the data AXI4 interface to external memory. The write also updates the cached data if the target address word is in the cache (that is, the write is a cache hit). The store completes immediately, unless the data AXI4 interface 32-word FIFO is full. The store completes immediately, unless the data AXI4 interface 32-word FIFO is full. A write cache-miss does not load the associated cache line into the cache.

With the write-back protocol, a FENCE.I instruction flushes all dirty cache locations and invalidates all other locations. The processor waits while invalidation is in progress.

With the write-through protocol, a FENCE.I instruction invalidates all cache locations. In 3-, 4-, and 5-stage pipelines, processor execution continues during invalidation, and accesses in cacheable regions bypass the cache while invalidation is in progress. In this case, additional FENCE.I instructions issued during this interval have no effect.

A load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (that is, on a cache hit) the requested data is retrieved from the cache. If it is not (that is, on a cache miss), the address is requested over the data AXI4 interface using a burst read, and the processor pipeline stalls until the cache line associated with the requested address is returned from the external memory controller.

If the address is non-cacheable, the cache controller ignores the instruction and lets the M_AXI_DP or DLMB complete the request.

The parameter C_DCACHE_DATA_WIDTH determines the bus data width, either 32 bits, an entire cache line (128, 256, or 512 bits), or 512 bits.

When C_FAULT_TOLERANT is set to 1 and write-through protocol is used, a cache miss also occurs if a parity error is detected in the tag or data block RAM.

The following table summarizes all types of accesses issued by the data cache AXI4 interface.