MicroBlaze V supports cache coherency, as well as
invalidation of caches and translation look-aside buffers, in hardware using the AXI
Coherency Extension (ACE) defined in the AMBA AXI and ACE Protocol
Specification (Arm IHI 0022H). The coherency support is enabled when the
parameter C_INTERCONNECT is set to 3 (ACE).
Using ACE ensures coherency between the caches of all MicroBlaze V processors in the coherency domain. The peripheral ports (AXI_IP, AXI_DP) and local memory (ILMB, DLMB) are outside the coherency domain.
Coherency is not supported with write-back data cache, wide cache interfaces (more than 32-bit data), instruction cache streams, or instruction cache victims.