Each slice receives six GPIO signals and two TDD signals from the SOM. The GPIO signals can be used for routing real-time control signals from the ZCU device to the slices. These signals can also be generated within the SOM PL logic and are time-synchronized with the frame sync signal. This is typically used for the mMIMO system for timing control. On the FB slices, these signals can be used to control an FB RF switch to select the FB signal to feed the slices (the FB RF switch is not part of this kit). This is typically used for mMIMO system for timing control. This FB MUX switch can be controlled by the XRF4 GUI or from the DFE system running on the ZCU device.
The following table describes the system controller slice GPIO interfaces.
| Interface Name | Bit Width | Connection | Description |
|---|---|---|---|
| SL<3:0>_GPIO | 6 | SOM to RX slices | GPIO for four RX slices. |
| SL4_GPIO | 6 | SOM to FB slice | GPIO for FB slice 4. Can be used for FB RF switch control. |
| SL<8:5>_GPIO | 6 | SOM to TX slices | GPIO for four TX slices. |
| SL<8:0>_TDD0 | 1 | SOM to slice | TDD0 signals for nine slices originating from the ZCU DFE system. |
| SL<8:0>_TDD1 | 1 | SOM to slice | TDD1 signal for nine slices originating from the ZCU DFE system. |
The following figure shows the GPIO interface map.